文件名称:resolutionquartusII

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 5.95mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 权*
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用verilog编写的分辨率提高的源代码 采用双线性插值-Written resolution with the verilog source code to improve the use of bilinear interpolation
相关搜索: bilinear
interpolation
verilog

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下载文件列表

分辨率quartusII\双线性\双线性插值程序\altdpram0.bsf

...............\......\..............\altdpram0.qip

...............\......\..............\altdpram0.tdf

...............\......\..............\altdpram0_wave0.jpg

...............\......\..............\altdpram0_wave1.jpg

...............\......\..............\altdpram0_waveforms.html

...............\......\..............\altdpram1.bsf

...............\......\..............\altdpram1.qip

...............\......\..............\altdpram1.tdf

...............\......\..............\altdpram1_wave0.jpg

...............\......\..............\altdpram1_wave1.jpg

...............\......\..............\altdpram1_waveforms.html

...............\......\..............\altdpram2.bsf

...............\......\..............\altdpram2.qip

...............\......\..............\altdpram2.tdf

...............\......\..............\altdpram2_wave0.jpg

...............\......\..............\altdpram2_wave1.jpg

...............\......\..............\altdpram2_waveforms.html

...............\......\..............\altpll0.bsf

...............\......\..............\altpll0.ppf

...............\......\..............\altpll0.qip

...............\......\..............\altpll0.tdf

...............\......\..............\altpll0_wave0.jpg

...............\......\..............\altpll0_waveforms.html

...............\......\..............\clk_fp.bsf

...............\......\..............\clk_fp.v

...............\......\..............\clk_fp.v.bak

...............\......\..............\clk_select.bsf

...............\......\..............\clk_select.v

...............\......\..............\clk_select.v.bak

...............\......\..............\final_out.v

...............\......\..............\final_output.bsf

...............\......\..............\final_output.v

...............\......\..............\final_output.v.bak

...............\......\..............\inline_polation.bsf

...............\......\..............\inline_polation.v.bak

...............\......\..............\line_all_over.bsf

...............\......\..............\line_all_over.v

...............\......\..............\line_all_over.v.bak

...............\......\..............\lpm_fifo_dc0.bsf

...............\......\..............\lpm_fifo_dc0.qip

...............\......\..............\lpm_fifo_dc0.tdf

...............\......\..............\lpm_fifo_dc0_wave0.jpg

...............\......\..............\lpm_fifo_dc0_wave1.jpg

...............\......\..............\lpm_fifo_dc0_waveforms.html

...............\......\..............\polation_betweenline.bsf

...............\......\..............\polation_betweenline.v

...............\......\..............\polation_betweenline.v.bak

...............\......\..............\polation_inline.bsf

...............\......\..............\polation_inline.v

...............\......\..............\polation_inline.v.bak

...............\......\..............\polation_inline_first.bsf

...............\......\..............\polation_inline_first.v

...............\......\..............\polation_inline_first.v.bak

...............\......\..............\RAM_aderess.bsf

...............\......\..............\RAM_aderess.v

...............\......\..............\RAM_aderess.v.bak

...............\......\..............\RAM_en_address.bsf

...............\......\..............\RAM_en_address.v

...............\......\..............\rden.v

...............\......\..............\rden.v.bak

...............\......\..............\resolution_module.bdf

...............\......\..............\resolution_top.bdf

...............\......\..............\resolution_top.bsf

...............\......\..............\UNUSED

...............\......\..............\Verilog1.v

...............\......\..............\Verilog1.v.bak

...............\......\..............\wr_clk.asm.rpt

...............\......\..............\wr_clk.bsf

...............\......\..............\wr_clk.done

...............\......\..............\wr_clk.fit.rpt

...............\......\..............\wr_clk.fit.smsg

...............\......\..............\wr_clk.fit.summary

...............\......\..............\wr_clk.flow.rpt

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