文件名称:ddr_ddr2_sdram9.0
介绍说明－－下载内容均来自于网络，请自行研究使用
altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
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下载文件列表
lib\.recurs
...\auk_ddr2_init.ocp
...\auk_ddr2_init.vhd
...\auk_ddr_avalon_if.vhd
...\auk_ddr_bank_details.vhd
...\auk_ddr_controller.vhd
...\auk_ddr_functions.vhd
...\auk_ddr_init.ocp
...\auk_ddr_init.vhd
...\auk_ddr_input_buf.vhd
...\auk_ddr_tb_functions.vhd
...\auk_ddr_timers.vhd
...\cycloneii_dsp_rev_a_pins.tcl
...\cycloneii_nios_pins.tcl
...\cycloneii_pci_rev_a_pins.tcl
...\cyclone_mem_board_pins.tcl
...\ddr2_sdram_controller_wizard.lst
...\ddr_sdram_controller_wizard.lst
...\example_lfsr8.v
...\example_lfsr8.vhd
...\ip_toolbench\auk_ddr_sdram_rtl_vsim.tcl
...\............\config.ptf
...\............\ddr2_sdram_controller.jar
...\............\ddr_sdram_controller.jar
...\............\e_auk_ddr_ctrl.pm
...\............\e_lpm_altddio_bidir.pm
...\............\e_lpm_altddio_out.pm
...\............\e_lpm_stratixii_dll.pm
...\............\e_lpm_stratixii_io.pm
...\............\e_lpm_stratix_dll.pm
...\............\e_lpm_stratix_io.pm
...\............\generate_ddr_datapath
...\............\generic_ddr2_sdram.vhd
...\............\generic_ddr_dimm_model.vhd
...\............\generic_ddr_sdram.vhd
...\............\wave.do
...\............\write_byte_groups.pm
...\............\write_datapath.pm
...\............\write_ddr_clk_gen.pm
...\............\write_ddr_dll_gen.pm
...\............\write_ddr_sdram.pm
...\............\write_ddr_sdram_controller.pm
...\............\write_example_driver.pm
...\............\write_example_instance.pm
...\sopc_builder\ddr2_sdram_component\class.ptf
...\............\....................\core_add_program.pl
...\............\....................\generate_ddr_sim_model.pl
...\............\....................\iptb_deployment.pl
...\............\..._sdram_component\class.ptf
...\............\...................\core_add_program.pl
...\............\...................\generate_ddr_sim_model.pl
...\............\...................\iptb_deployment.pl
...\stratixii_hsio_pins.tcl
...\stratixii_pci_rev_a_pins.tcl
...\stratixii_s2mb2_dimm_pins.tcl
...\stratix_pci_rev_b_pins.tcl
...\stratix_smb1_dimm_pins.tcl
...\stratix_smb2_dimm_pins.tcl
...\tcl\data.tcl
...\...\dotty.tcl
...\...\dqsfbc.tcl
...\...\extract.tcl
...\...\file.tcl
...\...\flowtools.tcl
...\...\legacy.tcl
...\...\log.tcl
...\...\messages.tcl
...\...\mwinterface.tcl
...\...\nondqsfbc.tcl
...\...\paths.tcl
...\...\pcinterface.tcl
...\...\phasesel.tcl
...\...\pkgIndex.tcl
...\...\s2dqs.tcl
...\...\settings.tcl
...\...\type.tcl
...\...\utils.tcl
...\twister_rev_b_pins.tcl
...\sopc_builder\ddr2_sdram_component
...\............\ddr_sdram_component
...\ip_toolbench
...\sopc_builder
...\tcl
lib
...\auk_ddr2_init.ocp
...\auk_ddr2_init.vhd
...\auk_ddr_avalon_if.vhd
...\auk_ddr_bank_details.vhd
...\auk_ddr_controller.vhd
...\auk_ddr_functions.vhd
...\auk_ddr_init.ocp
...\auk_ddr_init.vhd
...\auk_ddr_input_buf.vhd
...\auk_ddr_tb_functions.vhd
...\auk_ddr_timers.vhd
...\cycloneii_dsp_rev_a_pins.tcl
...\cycloneii_nios_pins.tcl
...\cycloneii_pci_rev_a_pins.tcl
...\cyclone_mem_board_pins.tcl
...\ddr2_sdram_controller_wizard.lst
...\ddr_sdram_controller_wizard.lst
...\example_lfsr8.v
...\example_lfsr8.vhd
...\ip_toolbench\auk_ddr_sdram_rtl_vsim.tcl
...\............\config.ptf
...\............\ddr2_sdram_controller.jar
...\............\ddr_sdram_controller.jar
...\............\e_auk_ddr_ctrl.pm
...\............\e_lpm_altddio_bidir.pm
...\............\e_lpm_altddio_out.pm
...\............\e_lpm_stratixii_dll.pm
...\............\e_lpm_stratixii_io.pm
...\............\e_lpm_stratix_dll.pm
...\............\e_lpm_stratix_io.pm
...\............\generate_ddr_datapath
...\............\generic_ddr2_sdram.vhd
...\............\generic_ddr_dimm_model.vhd
...\............\generic_ddr_sdram.vhd
...\............\wave.do
...\............\write_byte_groups.pm
...\............\write_datapath.pm
...\............\write_ddr_clk_gen.pm
...\............\write_ddr_dll_gen.pm
...\............\write_ddr_sdram.pm
...\............\write_ddr_sdram_controller.pm
...\............\write_example_driver.pm
...\............\write_example_instance.pm
...\sopc_builder\ddr2_sdram_component\class.ptf
...\............\....................\core_add_program.pl
...\............\....................\generate_ddr_sim_model.pl
...\............\....................\iptb_deployment.pl
...\............\..._sdram_component\class.ptf
...\............\...................\core_add_program.pl
...\............\...................\generate_ddr_sim_model.pl
...\............\...................\iptb_deployment.pl
...\stratixii_hsio_pins.tcl
...\stratixii_pci_rev_a_pins.tcl
...\stratixii_s2mb2_dimm_pins.tcl
...\stratix_pci_rev_b_pins.tcl
...\stratix_smb1_dimm_pins.tcl
...\stratix_smb2_dimm_pins.tcl
...\tcl\data.tcl
...\...\dotty.tcl
...\...\dqsfbc.tcl
...\...\extract.tcl
...\...\file.tcl
...\...\flowtools.tcl
...\...\legacy.tcl
...\...\log.tcl
...\...\messages.tcl
...\...\mwinterface.tcl
...\...\nondqsfbc.tcl
...\...\paths.tcl
...\...\pcinterface.tcl
...\...\phasesel.tcl
...\...\pkgIndex.tcl
...\...\s2dqs.tcl
...\...\settings.tcl
...\...\type.tcl
...\...\utils.tcl
...\twister_rev_b_pins.tcl
...\sopc_builder\ddr2_sdram_component
...\............\ddr_sdram_component
...\ip_toolbench
...\sopc_builder
...\tcl
lib