文件名称:AlteraSDR-SDRAM
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 792kb
- 下载次数：
- 0次
- 提 供 者：
- mache*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
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vhdl
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下载文件列表
doc
...\readme.txt
...\sdr_sdram.pdf
model
.....\mt48lc8m16a2.v
route
.....\PLL1.v
.....\sdr_sdram.csf
.....\sdr_sdram.esf
.....\sdr_sdram.vqm
simulation
..........\modelsim.ini
..........\readme.txt
..........\sdr_sdram_tb.v
..........\work
..........\....\altclklock
..........\....\..........\verilog.psm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\command
..........\....\.......\verilog.psm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\control_interface
..........\....\.................\verilog.psm
..........\....\.................\_primary.dat
..........\....\.................\_primary.vhd
..........\....\mt48lc8m16a2
..........\....\............\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\pll1
..........\....\....\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\sdr_data_path
..........\....\.............\verilog.psm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\sdr_sdram
..........\....\.........\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\sdr_sdram_tb
..........\....\............\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\_info
source
......\altclklock.v
......\Command.v
......\compile_all.v
......\control_interface.v
......\Params.v
......\PLL1.v
......\sdr_data_path.v
......\sdr_sdram.v
synthesis
.........\synplicity
.........\..........\sdr_sdram.prj
...\readme.txt
...\sdr_sdram.pdf
model
.....\mt48lc8m16a2.v
route
.....\PLL1.v
.....\sdr_sdram.csf
.....\sdr_sdram.esf
.....\sdr_sdram.vqm
simulation
..........\modelsim.ini
..........\readme.txt
..........\sdr_sdram_tb.v
..........\work
..........\....\altclklock
..........\....\..........\verilog.psm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\command
..........\....\.......\verilog.psm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\control_interface
..........\....\.................\verilog.psm
..........\....\.................\_primary.dat
..........\....\.................\_primary.vhd
..........\....\mt48lc8m16a2
..........\....\............\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\pll1
..........\....\....\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\sdr_data_path
..........\....\.............\verilog.psm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\sdr_sdram
..........\....\.........\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\sdr_sdram_tb
..........\....\............\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\_info
source
......\altclklock.v
......\Command.v
......\compile_all.v
......\control_interface.v
......\Params.v
......\PLL1.v
......\sdr_data_path.v
......\sdr_sdram.v
synthesis
.........\synplicity
.........\..........\sdr_sdram.prj