文件名称:FIFO
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 31kb
- 下载次数：
- 0次
- 提 供 者：
- yasir******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
相关搜索： fifo
modelsim
fifo
verilog
modelsim
ise
fifo
verilog
dsp
verilog
FIFO
Verilog
FIFO
code
dsp
fifo
FIFO
VHDL
ISE
FIFO
verilog
modelsim
fifo
verilog
modelsim
ise
fifo
verilog
dsp
verilog
FIFO
Verilog
FIFO
code
dsp
fifo
FIFO
VHDL
ISE
FIFO
verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FIFO
....\bench
....\.....\fifo_tb.v
....\.....\tasks
....\.....\.....\comp_data.v
....\.....\.....\initialize_sys.v
....\.....\.....\mk_infile.v
....\.....\.....\rd_data.v
....\.....\.....\reset_sys.v
....\.....\.....\wrt_data.v
....\rtl
....\...\fifo_top.v
....\...\ram_blk.v
....\sim
....\...\fifo.cr.mti
....\...\fifo.mpf
....\...\output_files
....\...\............\ch_data.txt
....\...\............\compare_data.txt
....\...\............\data_rd.txt
....\...\parameters.v
....\...\work
....\...\....\fifo_tb
....\...\....\.......\verilog.asm
....\...\....\.......\_primary.dat
....\...\....\.......\_primary.vhd
....\...\....\fifo_top
....\...\....\........\verilog.asm
....\...\....\........\_primary.dat
....\...\....\........\_primary.vhd
....\...\....\ram_32x8
....\...\....\........\verilog.asm
....\...\....\........\_primary.dat
....\...\....\........\_primary.vhd
....\...\....\ram_blk
....\...\....\.......\verilog.asm
....\...\....\.......\_primary.dat
....\...\....\.......\_primary.vhd
....\...\....\_info
....\bench
....\.....\fifo_tb.v
....\.....\tasks
....\.....\.....\comp_data.v
....\.....\.....\initialize_sys.v
....\.....\.....\mk_infile.v
....\.....\.....\rd_data.v
....\.....\.....\reset_sys.v
....\.....\.....\wrt_data.v
....\rtl
....\...\fifo_top.v
....\...\ram_blk.v
....\sim
....\...\fifo.cr.mti
....\...\fifo.mpf
....\...\output_files
....\...\............\ch_data.txt
....\...\............\compare_data.txt
....\...\............\data_rd.txt
....\...\parameters.v
....\...\work
....\...\....\fifo_tb
....\...\....\.......\verilog.asm
....\...\....\.......\_primary.dat
....\...\....\.......\_primary.vhd
....\...\....\fifo_top
....\...\....\........\verilog.asm
....\...\....\........\_primary.dat
....\...\....\........\_primary.vhd
....\...\....\ram_32x8
....\...\....\........\verilog.asm
....\...\....\........\_primary.dat
....\...\....\........\_primary.vhd
....\...\....\ram_blk
....\...\....\.......\verilog.asm
....\...\....\.......\_primary.dat
....\...\....\.......\_primary.vhd
....\...\....\_info