文件名称:ref-ddr-sdram-vhdl
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本程序是DDR SDRAM控制器的VHDL程序,由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
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压缩包 : 101259362ref-ddr-sdram-vhdl.rar 列表 ref-ddr-sdram-vhdl\readme.txt ref-ddr-sdram-vhdl\synthesis\synplicity\ddr_sdram.prj ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.srm ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.srr ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.srs ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.tcl ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.tlg ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.vqm ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram.xrf ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram_cons.tcl ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1\ddr_sdram_rm.tcl ref-ddr-sdram-vhdl\synthesis\synplicity\rev_1 ref-ddr-sdram-vhdl\synthesis\synplicity ref-ddr-sdram-vhdl\synthesis ref-ddr-sdram-vhdl\source\ddr_command.vhd ref-ddr-sdram-vhdl\source\ddr_control_interface.vhd ref-ddr-sdram-vhdl\source\ddr_data_path.vhd ref-ddr-sdram-vhdl\source\ddr_sdram.vhd ref-ddr-sdram-vhdl\source ref-ddr-sdram-vhdl\simulation\APEX20KE_MF.VHD ref-ddr-sdram-vhdl\simulation\ddr_command.vhd ref-ddr-sdram-vhdl\simulation\ddr_control_interface.vhd ref-ddr-sdram-vhdl\simulation\ddr_data_path.vhd ref-ddr-sdram-vhdl\simulation\ddr_sdram.vhd ref-ddr-sdram-vhdl\simulation\ddr_sdram_tb.vhd ref-ddr-sdram-vhdl\simulation\io_utils.vhd ref-ddr-sdram-vhdl\simulation\lpm_pack.vhd ref-ddr-sdram-vhdl\simulation\modelsim.ini ref-ddr-sdram-vhdl\simulation\mt46v4m16.vhd ref-ddr-sdram-vhdl\simulation\mti_pkg.vhd ref-ddr-sdram-vhdl\simulation\pll1.vhd ref-ddr-sdram-vhdl\simulation\readme.txt ref-ddr-sdram-vhdl\simulation\stdlogar.vhd ref-ddr-sdram-vhdl\simulation\util1164.vhd ref-ddr-sdram-vhdl\simulation\wave.do ref-ddr-sdram-vhdl\simulation\work\_info ref-ddr-sdram-vhdl\simulation\work\util_1164\body.dat ref-ddr-sdram-vhdl\simulation\work\util_1164\body.psm ref-ddr-sdram-vhdl\simulation\work\util_1164\_primary.dat ref-ddr-sdram-vhdl\simulation\work\util_1164\_vhdl.psm ref-ddr-sdram-vhdl\simulation\work\util_1164 ref-ddr-sdram-vhdl\simulation\work\std_logic_arith\body.dat ref-ddr-sdram-vhdl\simulation\work\std_logic_arith\body.psm ref-ddr-sdram-vhdl\simulation\work\std_logic_arith\_primary.dat ref-ddr-sdram-vhdl\simulation\work\std_logic_arith\_vhdl.psm ref-ddr-sdram-vhdl\simulation\work\std_logic_arith ref-ddr-sdram-vhdl\simulation\work\pll1\syn.dat ref-ddr-sdram-vhdl\simulation\work\pll1\syn.psm ref-ddr-sdram-vhdl\simulation\work\pll1\_primary.dat ref-ddr-sdram-vhdl\simulation\work\pll1 ref-ddr-sdram-vhdl\simulation\work\mti_pkg\body.dat ref-ddr-sdram-vhdl\simulation\work\mti_pkg\body.psm ref-ddr-sdram-vhdl\simulation\work\mti_pkg\_primary.dat ref-ddr-sdram-vhdl\simulation\work\mti_pkg\_vhdl.psm ref-ddr-sdram-vhdl\simulation\work\mti_pkg ref-ddr-sdram-vhdl\simulation\work\mt46v4m16\behave.dat ref-ddr-sdram-vhdl\simulation\work\mt46v4m16\behave.psm ref-ddr-sdram-vhdl\simulation\work\mt46v4m16\_primary.dat ref-ddr-sdram-vhdl\simulation\work\mt46v4m16 ref-ddr-sdram-vhdl\simulation\work\lpm_components\body.dat ref-ddr-sdram-vhdl\simulation\work\lpm_components\body.psm ref-ddr-sdram-vhdl\simulation\work\lpm_components\_primary.dat ref-ddr-sdram-vhdl\simulation\work\lpm_components\_vhdl.psm ref-ddr-sdram-vhdl\simulation\work\lpm_components ref-ddr-sdram-vhdl\simulation\work\io_utils\body.dat ref-ddr-sdram-vhdl\simulation\work\io_utils\body.psm ref-ddr-sdram-vhdl\simulation\work\io_utils\_primary.dat ref-ddr-sdram-vhdl\simulation\work\io_utils\_vhdl.psm ref-ddr-sdram-vhdl\simulation\work\io_utils ref-ddr-sdram-vhdl\simulation\work\ddr_sdram_tb\rtl.dat ref-ddr-sdram-vhdl\simulation\work\ddr_sdram_tb\rtl.psm ref-ddr-sdram-vhdl\simulation\work\ddr_sdram_tb\_primary.dat ref-ddr-sdram-vhdl\simulation\work\ddr_sdram_tb ref-ddr-sdram-vhdl\simulation\work\ddr_sdram\rtl.dat ref-ddr-sdram-vhdl\simulation\work\ddr_sdram\rtl.psm ref-ddr-sdram-vhdl\simulation\work\ddr_sdram\_primary.dat ref-ddr-sdram-vhdl\simulation\work\ddr_sdram ref-ddr-sdram-vhdl\simulation\work\ddr_data_path\rtl.dat ref-ddr-sdram-vhdl\simulation\work\ddr_data_path\rtl.psm ref-ddr-sdram-vhdl\simulation\work\ddr_data_path\_primary.dat ref-ddr-sdram-vhdl\simulation\work\ddr_data_path ref-ddr-sdram-vhdl\simulation\work\ddr_control_interface\rtl.dat ref-ddr-sdram-vhdl\simulation\work\ddr_control_interface\rtl.psm ref-ddr-sdram-vhdl\simulation\work\ddr_control_interface\_primary.dat ref-ddr-sdram-vhdl\simulation\work\ddr_control_interface ref-ddr-sdram-vhdl\simulation\work\ddr_command\rtl.dat ref-ddr-sdram-vhdl\simulation\work\ddr_command\rtl.psm ref-ddr-sdram-vhdl\simulation\work\ddr_command\_primary.dat ref-ddr-sdram-vhdl\simulation\work\ddr_command ref-ddr-sdram-vhdl\simulation\work\control_interface\rtl.dat ref-ddr-sdram-vhdl\simulation\work\control_interface\rtl.psm ref-ddr-sdram-vhdl\simulation\work\control_interface\_primary.dat ref-ddr-sdram-vhdl\simulation\work\control_interface ref-ddr-sdram-vhdl\simulation\work\command\rtl.dat ref-ddr-sdram-vhdl\simulation\work\command\rtl.psm ref-ddr-sdram-vhdl\simulation\work\command\_primary.dat ref-ddr-sdram-vhdl\simulation\work\command ref-ddr-sdram-vhdl\simulation\work\altlvds_tx\behavior.dat ref-ddr-sdram-vhdl\simulation\work\altlvds_tx\behavior.psm ref-ddr-sdram-vhdl\simulation\work\altlvds_tx\_primary.dat ref-ddr-sdram-vhdl\simulation\work\altlvds_tx ref-ddr-sdram-vhdl\simulation\work\altlvds_rx\behavior.dat ref-ddr-sdram-vhdl\simulation\work\altlvds_rx\behavior.psm ref-ddr-sdram-vhdl\simulation\work\altlvds_rx\_primary.dat ref-ddr-sdram-vhdl\simulation\work\altlvds_rx ref-ddr-sdram-vhdl\simulation\work\altclklock\behavior.dat ref-ddr-sdram-vhdl\simulation\work\altclklock\behavior.psm ref-ddr-sdram-vhdl\simulation\work\altclklock\_primary.dat ref-ddr-sdram-vhdl\simulation\work\altclklock ref-ddr-sdram-vhdl\simulation\work\altcam\behave.dat ref-ddr-sdram-vhdl\simulation\work\altcam\behave.psm ref-ddr-sdram-vhdl\simulation\work\altcam\_primary.dat ref-ddr-sdram-vhdl\simulation\work\altcam ref-ddr-sdram-vhdl\simulation\work ref-ddr-sdram-vhdl\simulation ref-ddr-sdram-vhdl\route\ddr_sdram.csf ref-ddr-sdram-vhdl\route\ddr_sdram.esf ref-ddr-sdram-vhdl\route\ddr_sdram.quartus ref-ddr-sdram-vhdl\route\ddr_sdram.vqm ref-ddr-sdram-vhdl\route\pll1.vhd ref-ddr-sdram-vhdl\route ref-ddr-sdram-vhdl\model\mt46v4m16.vhd ref-ddr-sdram-vhdl\model\mti_pkg.vhd ref-ddr-sdram-vhdl\model\transcript ref-ddr-sdram-vhdl\model ref-ddr-sdram-vhdl\doc ref-ddr-sdram-vhdl