文件名称:ALU
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VHDL实现cpu核心逻辑与运算单元模块的实现，完成4bit*4bit输入8bit输出的运算，可做加减乘除逻辑移位6种操作-the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
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下载文件列表
ALU - 复制
..........\.lso
..........\4adder.prj
..........\4adder.stx
..........\4adder.vhd
..........\4adder.xst
..........\4adder_vhdl.prj
..........\8adder.vhd
..........\add4_module.prj
..........\add4_module.stx
..........\add4_module.xst
..........\add4_module_vhdl.prj
..........\adder_4.prj
..........\adder_4.stx
..........\adder_4.xst
..........\adder_4_vhdl.prj
..........\adder_8.prj
..........\adder_8.stx
..........\adder_8.vhd
..........\adder_8.xst
..........\adder_8_vhd.udo
..........\adder_8_vhdl.prj
..........\ALU.ise
..........\ALU.ise_ISE_Backup
..........\ALU.ntrc_log
..........\ALU.restore
..........\baugh_wooley_multiplier.prj
..........\baugh_wooley_multiplier.stx
..........\baugh_wooley_multiplier.vhd
..........\baugh_wooley_multiplier.xst
..........\baugh_wooley_multiplier_summary.html
..........\baugh_wooley_multiplier_vhdl.prj
..........\divider.prj
..........\divider.stx
..........\divider.vhd
..........\divider.xst
..........\divider_vhdl.prj
..........\d_ff.prj
..........\d_ff.stx
..........\d_ff.vhd
..........\d_ff.xst
..........\d_ff4.vhd
..........\d_ff_vhdl.prj
..........\input.prj
..........\input.stx
..........\input.vhd
..........\input.xst
..........\input_vhdl.prj
..........\left_shifter.prj
..........\left_shifter.stx
..........\left_shifter.vhd
..........\left_shifter.xst
..........\left_shifter_vhdl.prj
..........\logic_operation.prj
..........\logic_operation.stx
..........\logic_operation.vhd
..........\logic_operation.xst
..........\logic_operation_vhdl.prj
..........\multi_test.vhd
..........\multi_test_vhd.udo
..........\pepExtractor.prj
..........\right_shifter.udo
..........\right_shifter.vhd
..........\shifter.vhd
..........\Signadder.prj
..........\Signadder.stx
..........\Signadder.udo
..........\Signadder.vhd
..........\Signadder.xst
..........\Signadder_vhdl.prj
..........\sigsub.vhd
..........\state_machine.vhd
..........\top_level.cmd_log
..........\top_level.lso
..........\top_level.ngc
..........\top_level.ngr
..........\top_level.prj
..........\top_level.stx
..........\top_level.syr
..........\top_level.vhd
..........\top_level.xst
..........\top_level_summary.html
..........\top_level_vhdl.prj
..........\top_tst.vhd
..........\top_tst_vhd.fdo
..........\top_tst_vhd.udo
..........\transcript
..........\vsim.wlf
..........\work
..........\....\adder_4
..........\....\.......\behavioral.asm
..........\....\.......\behavioral.dat
..........\....\.......\_primary.dat
..........\....\adder_8
..........\....\.......\behavioral.asm
..........\....\.......\behavioral.dat
..........\....\.......\_primary.dat
..........\....\adder_8_vhd
..........\....\...........\behavior.asm
..........\....\...........\behavior.dat
..........\.lso
..........\4adder.prj
..........\4adder.stx
..........\4adder.vhd
..........\4adder.xst
..........\4adder_vhdl.prj
..........\8adder.vhd
..........\add4_module.prj
..........\add4_module.stx
..........\add4_module.xst
..........\add4_module_vhdl.prj
..........\adder_4.prj
..........\adder_4.stx
..........\adder_4.xst
..........\adder_4_vhdl.prj
..........\adder_8.prj
..........\adder_8.stx
..........\adder_8.vhd
..........\adder_8.xst
..........\adder_8_vhd.udo
..........\adder_8_vhdl.prj
..........\ALU.ise
..........\ALU.ise_ISE_Backup
..........\ALU.ntrc_log
..........\ALU.restore
..........\baugh_wooley_multiplier.prj
..........\baugh_wooley_multiplier.stx
..........\baugh_wooley_multiplier.vhd
..........\baugh_wooley_multiplier.xst
..........\baugh_wooley_multiplier_summary.html
..........\baugh_wooley_multiplier_vhdl.prj
..........\divider.prj
..........\divider.stx
..........\divider.vhd
..........\divider.xst
..........\divider_vhdl.prj
..........\d_ff.prj
..........\d_ff.stx
..........\d_ff.vhd
..........\d_ff.xst
..........\d_ff4.vhd
..........\d_ff_vhdl.prj
..........\input.prj
..........\input.stx
..........\input.vhd
..........\input.xst
..........\input_vhdl.prj
..........\left_shifter.prj
..........\left_shifter.stx
..........\left_shifter.vhd
..........\left_shifter.xst
..........\left_shifter_vhdl.prj
..........\logic_operation.prj
..........\logic_operation.stx
..........\logic_operation.vhd
..........\logic_operation.xst
..........\logic_operation_vhdl.prj
..........\multi_test.vhd
..........\multi_test_vhd.udo
..........\pepExtractor.prj
..........\right_shifter.udo
..........\right_shifter.vhd
..........\shifter.vhd
..........\Signadder.prj
..........\Signadder.stx
..........\Signadder.udo
..........\Signadder.vhd
..........\Signadder.xst
..........\Signadder_vhdl.prj
..........\sigsub.vhd
..........\state_machine.vhd
..........\top_level.cmd_log
..........\top_level.lso
..........\top_level.ngc
..........\top_level.ngr
..........\top_level.prj
..........\top_level.stx
..........\top_level.syr
..........\top_level.vhd
..........\top_level.xst
..........\top_level_summary.html
..........\top_level_vhdl.prj
..........\top_tst.vhd
..........\top_tst_vhd.fdo
..........\top_tst_vhd.udo
..........\transcript
..........\vsim.wlf
..........\work
..........\....\adder_4
..........\....\.......\behavioral.asm
..........\....\.......\behavioral.dat
..........\....\.......\_primary.dat
..........\....\adder_8
..........\....\.......\behavioral.asm
..........\....\.......\behavioral.dat
..........\....\.......\_primary.dat
..........\....\adder_8_vhd
..........\....\...........\behavior.asm
..........\....\...........\behavior.dat