文件名称:8051core-Verilog
- 所属分类：
- 其他嵌入式/单片机内容
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 52kb
- 下载次数：
- 0次
- 提 供 者：
- 韩*
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
这里有verilog编写的8051ipcore 谁要啊?-Verilog prepared here has 8051ipcore who ah?
(系统自动生成,下载前可以参看下载内容)
下载文件列表
8051core-Verilog
................\8051core-Verilog
................\................\Acc.v
................\................\All.v
................\................\Alu.v
................\................\alu_src1_sel.v
................\................\alu_src2_sel.v
................\................\alu_src3_sel.v
................\................\Comp.v
................\................\cy_select.v
................\................\Decoder.v
................\................\Defines.v
................\................\Divide.v
................\................\Dptr.v
................\................\ext_addr_sel.v
................\................\immediate_sel.v
................\................\IndiAddr.v
................\................\Make
................\................\Multiply.v
................\................\op_select.v
................\................\Pc.v
................\................\Port_out.v
................\................\Psw.v
................\................\Ram.v
................\................\ram_rd_sel.v
................\................\Ram_sel.v
................\................\ram_wr_sel.v
................\................\Reg1.v
................\................\Reg2.v
................\................\Reg3.v
................\................\Reg4.v
................\................\Reg5.v
................\................\Reg8.v
................\................\Reg8r.v
................\................\Rom.v
................\................\rom_addr_sel.v
................\................\Sp.v
................\................\Tb_all.v
................\................\transcript
................\8051core-Verilog
................\................\Acc.v
................\................\All.v
................\................\Alu.v
................\................\alu_src1_sel.v
................\................\alu_src2_sel.v
................\................\alu_src3_sel.v
................\................\Comp.v
................\................\cy_select.v
................\................\Decoder.v
................\................\Defines.v
................\................\Divide.v
................\................\Dptr.v
................\................\ext_addr_sel.v
................\................\immediate_sel.v
................\................\IndiAddr.v
................\................\Make
................\................\Multiply.v
................\................\op_select.v
................\................\Pc.v
................\................\Port_out.v
................\................\Psw.v
................\................\Ram.v
................\................\ram_rd_sel.v
................\................\Ram_sel.v
................\................\ram_wr_sel.v
................\................\Reg1.v
................\................\Reg2.v
................\................\Reg3.v
................\................\Reg4.v
................\................\Reg5.v
................\................\Reg8.v
................\................\Reg8r.v
................\................\Rom.v
................\................\rom_addr_sel.v
................\................\Sp.v
................\................\Tb_all.v
................\................\transcript