文件名称:uart_regs
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 379kb
- 下载次数：
- 0次
- 提 供 者：
- liuji******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_regs
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs.eco.cdb
.........\...\..\uart_regs.sld_design_entry.sci
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\..\wed.wsf
.........\...\sim.cfg
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
.........\...\.......\uart_regs_h.vwf
.........\...\.......\uart_regs_pre.vwf
.........\...\parsim
.........\src
.........\...\sch
.........\...\...\db
.........\...\...\lpm_mux0.bsf
.........\...\...\lpm_mux0.v
.........\...\...\lpm_mux0_bb.v
.........\...\...\sch_exam.bdf
.........\...\seriesPort.v
.........\...\uart_defines.v
.........\...\uart_receiver.v
.........\...\uart_regs.v
.........\...\uart_transmitter.v
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs.eco.cdb
.........\...\..\uart_regs.sld_design_entry.sci
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\..\wed.wsf
.........\...\sim.cfg
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
.........\...\.......\uart_regs_h.vwf
.........\...\.......\uart_regs_pre.vwf
.........\...\parsim
.........\src
.........\...\sch
.........\...\...\db
.........\...\...\lpm_mux0.bsf
.........\...\...\lpm_mux0.v
.........\...\...\lpm_mux0_bb.v
.........\...\...\sch_exam.bdf
.........\...\seriesPort.v
.........\...\uart_defines.v
.........\...\uart_receiver.v
.........\...\uart_regs.v
.........\...\uart_transmitter.v