文件名称:AES_RTL
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使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
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下载文件列表
AES_RTL
.......\decrypt
.......\.......\AddRoundKey.v
.......\.......\decryption.v
.......\.......\Inv_MixColumns.v
.......\.......\Inv_ShiftRow.v
.......\.......\Inv_SubBytes.v
.......\.......\Inv_S_BOX.mif
.......\.......\Inv_S_BOX_2PORT.v
.......\encrypt
.......\.......\AddRoundKey.v
.......\.......\encryption.v
.......\.......\MixColumn.v
.......\.......\ShiftRow.v
.......\.......\SubBytes.v
.......\.......\S_BOX.mif
.......\.......\S_BOX_2PORT.v
.......\.......\S_BOX_2PORT_bb.v
.......\KeyExpansion.v
.......\decrypt
.......\.......\AddRoundKey.v
.......\.......\decryption.v
.......\.......\Inv_MixColumns.v
.......\.......\Inv_ShiftRow.v
.......\.......\Inv_SubBytes.v
.......\.......\Inv_S_BOX.mif
.......\.......\Inv_S_BOX_2PORT.v
.......\encrypt
.......\.......\AddRoundKey.v
.......\.......\encryption.v
.......\.......\MixColumn.v
.......\.......\ShiftRow.v
.......\.......\SubBytes.v
.......\.......\S_BOX.mif
.......\.......\S_BOX_2PORT.v
.......\.......\S_BOX_2PORT_bb.v
.......\KeyExpansion.v