文件名称:divider
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基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
相关搜索： divider
除法器
verilog
除法
除法
除法
VERILOG
SRT
div
verilog
Verilog
divider
unsigned
verilog
verilog
srt
srt-2
algorithm
除法器
verilog
除法
除法
除法
VERILOG
SRT
div
verilog
Verilog
divider
unsigned
verilog
verilog
srt
srt-2
algorithm
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下载文件列表
divider
.......\divider.v
.......\div_ctl.v
.......\div_datapath.v
.......\div_tb.v
.......\read me.txt
.......\divider.v
.......\div_ctl.v
.......\div_datapath.v
.......\div_tb.v
.......\read me.txt