文件名称:除法器
介绍说明－－下载内容均来自于网络，请自行研究使用
通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。
设计平台：MaxPlusII
压缩文件内有详细设计报告
-by using Hardware Descr iption Language (VHDL) Descr iption division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
设计平台：MaxPlusII
压缩文件内有详细设计报告
-by using Hardware Descr iption Language (VHDL) Descr iption division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
(系统自动生成,下载前可以参看下载内容)
下载文件列表
除法器
......\div.acf
......\div.fit
......\div.hif
......\div.mmf
......\div.ndb
......\div.pin
......\div.pof
......\div.rpt
......\div.scf
......\div.snf
......\DIV.sym
......\div.vhd
......\LIB.DLS
......\U0380056.DLS
......\U2871323.DLS
......\U7471229.DLS
除法器设计报告.doc
......\div.acf
......\div.fit
......\div.hif
......\div.mmf
......\div.ndb
......\div.pin
......\div.pof
......\div.rpt
......\div.scf
......\div.snf
......\DIV.sym
......\div.vhd
......\LIB.DLS
......\U0380056.DLS
......\U2871323.DLS
......\U7471229.DLS
除法器设计报告.doc