文件名称:filter 代码
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用verilog实现滤波器的功能，通过软件综合仿真，在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
filter
......\basicfir.fda
......\filter.vhd
......\filter_tb.vhd
......\vsim.wlf
......\work
......\....\filter
......\....\......\rtl.asm
......\....\......\rtl.dat
......\....\......\_primary.dat
......\....\filter_tb
......\....\.........\test.asm
......\....\.........\test.dat
......\....\.........\_primary.dat
......\....\_info
......\basicfir.fda
......\filter.vhd
......\filter_tb.vhd
......\vsim.wlf
......\work
......\....\filter
......\....\......\rtl.asm
......\....\......\rtl.dat
......\....\......\_primary.dat
......\....\filter_tb
......\....\.........\test.asm
......\....\.........\test.dat
......\....\.........\_primary.dat
......\....\_info