文件名称:signal_cpu_sort
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 8kb
- 下载次数：
- 0次
- 提 供 者：
- 張**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction.
The code has contain combination circuit and sequenial circuit.
CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
The code has contain combination circuit and sequenial circuit.
CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
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下载文件列表
signal_cpu_sort
...............\Add.v
...............\Alu.v
...............\Alu_control.v
...............\Control.v
...............\Data_memory.v
...............\Instruction_memory.v
...............\Line_control.v
...............\Pc.v
...............\Registers.v
...............\Sign_extend.v
...............\Single_cycle_cpu.v
...............\test.prj
...............\test.v
...............\testbranch.v
...............\Add.v
...............\Alu.v
...............\Alu_control.v
...............\Control.v
...............\Data_memory.v
...............\Instruction_memory.v
...............\Line_control.v
...............\Pc.v
...............\Registers.v
...............\Sign_extend.v
...............\Single_cycle_cpu.v
...............\test.prj
...............\test.v
...............\testbranch.v