文件名称:i2c(FPGA)
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
相关搜索： I2C
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(系统自动生成,下载前可以参看下载内容)
下载文件列表
I2C
...\automake.log
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\I2C.npl
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl.v.bak
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl.v.bak
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_defines.v.bak
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top.v.bak
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\i2c_slave_model.v.bak
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\wb_master_model.v.bak
...\work
...\....\glbl
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\i2c_slave_model
...\....\...............\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\_info
...\xst
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg07
...\...\....\.....\i2c_master_bit_ctrl.bin
...\...\....\vlg5C
...\...\....\.....\i2c_master_byte_ctrl.bin
...\...\....\vlg67
...\...\....\.....\i2c_master_top.bin
...\__projnav
...\.........\coregen.rsp
...\.........\I2C.gfl
...\.........\I2C_flowplus.gfl
...\.........\i2c_master_bit_ctrl.xst
...\.........\i2c_master_byte_ctrl.xst
...\.........\i2c_master_top.xst
...\.........\runXst_tcl.rsp
...\.........\xst_sprjTOstx_tcl.rsp
...\__projnav.log
...\automake.log
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\I2C.npl
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl.v.bak
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl.v.bak
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_defines.v.bak
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top.v.bak
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\i2c_slave_model.v.bak
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\wb_master_model.v.bak
...\work
...\....\glbl
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\i2c_slave_model
...\....\...............\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\_info
...\xst
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg07
...\...\....\.....\i2c_master_bit_ctrl.bin
...\...\....\vlg5C
...\...\....\.....\i2c_master_byte_ctrl.bin
...\...\....\vlg67
...\...\....\.....\i2c_master_top.bin
...\__projnav
...\.........\coregen.rsp
...\.........\I2C.gfl
...\.........\I2C_flowplus.gfl
...\.........\i2c_master_bit_ctrl.xst
...\.........\i2c_master_byte_ctrl.xst
...\.........\i2c_master_top.xst
...\.........\runXst_tcl.rsp
...\.........\xst_sprjTOstx_tcl.rsp
...\__projnav.log