文件名称:Quaalu
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ALU算术逻辑单元的简单实现,利用VHDL语言编写,可进行加法,减法,以及位的左右移动,只需一个时钟脉冲-ALU arithmetic logic unit to achieve a simple, using VHDL language, can be additive, subtractive, and the place and move around only one clock pulse
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下载文件列表
alu
...\ceshi.fit.rpt
...\ceshi.fit.summary
...\ceshi.flow.rpt
...\ceshi.map.eqn
...\ceshi.map.rpt
...\ceshi.map.summary
...\ceshi.qpf
...\ceshi.qsf
...\ceshi.qws
...\ceshi.vhd
...\cmp_state.ini
...\db
...\..\add_sub_djh.tdf
...\..\ceshi.cbx.xml
...\..\ceshi.cmp.cdb
...\..\ceshi.cmp.hdb
...\..\ceshi.cmp.rdb
...\..\ceshi.db_info
...\..\ceshi.eco.cdb
...\..\ceshi.fit.qmsg
...\..\ceshi.hier_info
...\..\ceshi.hif
...\..\ceshi.map.cdb
...\..\ceshi.map.hdb
...\..\ceshi.map.qmsg
...\..\ceshi.pre_map.cdb
...\..\ceshi.pre_map.hdb
...\..\ceshi.psp
...\..\ceshi.rtlv.hdb
...\..\ceshi.rtlv_sg.cdb
...\..\ceshi.rtlv_sg_swap.cdb
...\..\ceshi.sgdiff.cdb
...\..\ceshi.sgdiff.hdb
...\..\ceshi.sld_design_entry.sci
...\..\ceshi.sld_design_entry_dsc.sci
...\..\ceshi.syn_hier_info
...\..\ceshi_cmp.qrpt
...\ceshi.fit.rpt
...\ceshi.fit.summary
...\ceshi.flow.rpt
...\ceshi.map.eqn
...\ceshi.map.rpt
...\ceshi.map.summary
...\ceshi.qpf
...\ceshi.qsf
...\ceshi.qws
...\ceshi.vhd
...\cmp_state.ini
...\db
...\..\add_sub_djh.tdf
...\..\ceshi.cbx.xml
...\..\ceshi.cmp.cdb
...\..\ceshi.cmp.hdb
...\..\ceshi.cmp.rdb
...\..\ceshi.db_info
...\..\ceshi.eco.cdb
...\..\ceshi.fit.qmsg
...\..\ceshi.hier_info
...\..\ceshi.hif
...\..\ceshi.map.cdb
...\..\ceshi.map.hdb
...\..\ceshi.map.qmsg
...\..\ceshi.pre_map.cdb
...\..\ceshi.pre_map.hdb
...\..\ceshi.psp
...\..\ceshi.rtlv.hdb
...\..\ceshi.rtlv_sg.cdb
...\..\ceshi.rtlv_sg_swap.cdb
...\..\ceshi.sgdiff.cdb
...\..\ceshi.sgdiff.hdb
...\..\ceshi.sld_design_entry.sci
...\..\ceshi.sld_design_entry_dsc.sci
...\..\ceshi.syn_hier_info
...\..\ceshi_cmp.qrpt