文件名称:Example-b8-1
介绍说明--下载内容均来自于网络,请自行研究使用
使用ModelSim对Altera设计进行功能仿真
对于没有使用到Altera的MegaWizard或LPM的设计而言,功能仿真比较简单,读者只需依据8.2.5小节描述的步骤依次执行即可,对于使用了MegaWizard或LPM的设计,则必需在仿真时指定相关的Altera库
对于没有使用到Altera的MegaWizard或LPM的设计而言,功能仿真比较简单,读者只需依据8.2.5小节描述的步骤依次执行即可,对于使用了MegaWizard或LPM的设计,则必需在仿真时指定相关的Altera库
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下载文件列表
压缩包 : 89346489example-b8-1.rar 列表 示例说明.doc Altera_lib_files\220model.txt Altera_lib_files\220model.v Altera_lib_files\220model.vhd Altera_lib_files\220model_87.vhd Altera_lib_files\220pack.vhd Altera_lib_files\altera_mf.txt Altera_lib_files\altera_mf.v Altera_lib_files\altera_mf.vhd Altera_lib_files\altera_mf_87.vhd Altera_lib_files\altera_mf_components.vhd Altera_lib_files\stratix_atoms.v Altera_lib_files\stratix_atoms.vhd Altera_lib_files\stratix_components.vhd func_sim\dpram8x32.v func_sim\func_sim.cr.mti func_sim\func_sim.mpf func_sim\func_sim_wave.wlf func_sim\pllx2.v func_sim\pll_ram.v func_sim\pll_ram_tb.v func_sim\transcript func_sim\vsim.wlf func_sim\wave.bmp func_sim\wave.do func_sim\work\dpram8x32\verilog.asm func_sim\work\dpram8x32\_primary.dat func_sim\work\dpram8x32\_primary.vhd func_sim\work\pllx2\verilog.asm func_sim\work\pllx2\_primary.dat func_sim\work\pllx2\_primary.vhd func_sim\work\pll_ram\verilog.asm func_sim\work\pll_ram\_primary.dat func_sim\work\pll_ram\_primary.vhd func_sim\work\pll_ram_tb\verilog.asm func_sim\work\pll_ram_tb\_primary.dat func_sim\work\pll_ram_tb\_primary.vhd func_sim\work\_info pll_ram\cmp_state.ini pll_ram\db\altsyncram_7bc1.tdf pll_ram\db\pll_ram(0).cnf.cdb pll_ram\db\pll_ram(0).cnf.hdb pll_ram\db\pll_ram(1).cnf.cdb pll_ram\db\pll_ram(1).cnf.hdb pll_ram\db\pll_ram(2).cnf.cdb pll_ram\db\pll_ram(2).cnf.hdb pll_ram\db\pll_ram(3).cnf.cdb pll_ram\db\pll_ram(3).cnf.hdb pll_ram\db\pll_ram(4).cnf.cdb pll_ram\db\pll_ram(4).cnf.hdb pll_ram\db\pll_ram(5).cnf.cdb pll_ram\db\pll_ram(5).cnf.hdb pll_ram\db\pll_ram(6).cnf.cdb pll_ram\db\pll_ram(6).cnf.hdb pll_ram\db\pll_ram(7).cnf.cdb pll_ram\db\pll_ram(7).cnf.hdb pll_ram\db\pll_ram.asm.qmsg pll_ram\db\pll_ram.cmp.cdb pll_ram\db\pll_ram.cmp.ddb pll_ram\db\pll_ram.cmp.hdb pll_ram\db\pll_ram.cmp.rdb pll_ram\db\pll_ram.cmp.tdb pll_ram\db\pll_ram.csf.qmsg pll_ram\db\pll_ram.db_info pll_ram\db\pll_ram.eda.qmsg pll_ram\db\pll_ram.fit.qmsg pll_ram\db\pll_ram.hif pll_ram\db\pll_ram.icc pll_ram\db\pll_ram.map.cdb pll_ram\db\pll_ram.map.hdb pll_ram\db\pll_ram.map.qmsg pll_ram\db\pll_ram.pll_ram.sld_design_entry.sci pll_ram\db\pll_ram.pre_map.hdb pll_ram\db\pll_ram.project.hdb pll_ram\db\pll_ram.rtlv.hdb pll_ram\db\pll_ram.rtlv_sg.cdb pll_ram\db\pll_ram.rtlv_sg_swap.cdb pll_ram\db\pll_ram.sgdiff.cdb pll_ram\db\pll_ram.sgdiff.hdb pll_ram\db\pll_ram.signalprobe.cdb pll_ram\db\pll_ram.tan.qmsg pll_ram\db\pll_ram_cmp.qrpt pll_ram\db\pll_ram_hier_info pll_ram\db\pll_ram_syn_hier_info pll_ram\dpram8x32.v pll_ram\pllx2.v pll_ram\pll_ram.asm.rpt pll_ram\pll_ram.done pll_ram\pll_ram.eda.rpt pll_ram\pll_ram.fit.eqn pll_ram\pll_ram.fit.rpt pll_ram\pll_ram.flow.rpt pll_ram\pll_ram.map.eqn pll_ram\pll_ram.map.rpt pll_ram\pll_ram.pin pll_ram\pll_ram.pof pll_ram\pll_ram.qpf pll_ram\pll_ram.qsf pll_ram\pll_ram.qws pll_ram\pll_ram.sof pll_ram\pll_ram.tan.rpt pll_ram\pll_ram.tan.summary pll_ram\pll_ram.v pll_ram\simulation\modelsim\pll_ram.vo pll_ram\simulation\modelsim\pll_ram_modelsim.xrf pll_ram\simulation\modelsim\pll_ram_v.sdo source\dpram8x32.v source\dpram8x32_bb.v source\dpram8x32_wave0.jpg source\dpram8x32_wave1.jpg source\dpram8x32_wave2.jpg source\dpram8x32_wave3.jpg source\dpram8x32_waveforms.html source\pllx2.v source\pllx2_bb.v source\pll_ram.v source\pll_ram_tb.v source\post-simulation\modelsim\pll_ram.vo source\post-simulation\modelsim\pll_ram_modelsim.xrf source\post-simulation\modelsim\pll_ram_v.sdo timing_sim\pll_ram.vo timing_sim\pll_ram_modelsim.xrf timing_sim\pll_ram_tb.v timing_sim\pll_ram_v.sdo timing_sim\timing_sim.cr.mti timing_sim\timing_sim.mpf timing_sim\transcript timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.vhd timing_sim\work\@m@f_pll_reg\verilog.asm timing_sim\work\@m@f_pll_reg\_primary.dat timing_sim\work\@m@f_pll_reg\_primary.vhd timing_sim\work\@m@f_ram7x20_syn\verilog.asm timing_sim\work\@m@f_ram7x20_syn\_primary.dat timing_sim\work\@m@f_ram7x20_syn\_primary.vhd timing_sim\work\@m@f_stratixii_pll\verilog.asm timing_sim\work\@m@f_stratixii_pll\_primary.dat timing_sim\work\@m@f_stratixii_pll\_primary.vhd timing_sim\work\@m@f_stratix_pll\verilog.asm timing_sim\work\@m@f_stratix_pll\_primary.dat timing_sim\work\@m@f_stratix_pll\_primary.vhd timing_sim\work\@p@r@i@m_@d@f@f@e\verilog.asm timing_sim\work\@p@r@i@m_@d@f@f@e\_primary.dat timing_sim\work\@p@r@i@m_@d@f@f@e\_primary.vhd timing_sim\work\alt3pram\verilog.asm timing_sim\work\alt3pram\_primary.dat timing_sim\work\alt3pram\_primary.vhd timing_sim\work\altaccumulate\verilog.asm timing_sim\work\altaccumulate\_primary.dat timing_sim\work\altaccumulate\_primary.vhd timing_sim\work\altcam\verilog.asm timing_sim\work\altcam\_primary.dat timing_sim\work\altcam\_primary.vhd timing_sim\work\altcdr_rx\verilog.asm timing_sim\work\altcdr_rx\_primary.dat timing_sim\work\altcdr_rx\_primary.vhd timing_sim\work\altcdr_tx\verilog.asm timing_sim\work\altcdr_tx\_primary.dat timing_sim\work\altcdr_tx\_primary.vhd timing_sim\work\altclklock\verilog.asm timing_sim\work\altclklock\_primary.dat timing_sim\work\altclklock\_primary.vhd timing_sim\work\altddio_bidir\verilog.asm timing_sim\work\altddio_bidir\_primary.dat timing_sim\work\altddio_bidir\_primary.vhd timing_sim\work\altddio_in\verilog.asm timing_sim\work\altddio_in\_primary.dat timing_sim\work\altddio_in\_primary.vhd timing_sim\work\altddio_out\verilog.asm timing_sim\work\altddio_out\_primary.dat timing_sim\work\altddio_out\_primary.vhd timing_sim\work\altdpram\verilog.asm timing_sim\work\altdpram\_primary.dat timing_sim\work\altdpram\_primary.vhd timing_sim\work\altfp_mult\verilog.asm timing_sim\work\altfp_mult\_primary.dat timing_sim\work\altfp_mult\_primary.vhd timing_sim\work\altlvds_rx\verilog.asm timing_sim\work\altlvds_rx\_primary.dat timing_sim\work\altlvds_rx\_primary.vhd timing_sim\work\altlvds_tx\verilog.asm timing_sim\work\altlvds_tx\_primary.dat timing_sim\work\altlvds_tx\_primary.vhd timing_sim\work\altmult_accum\verilog.asm timing_sim\work\altmult_accum\_primary.dat timing_sim\work\altmult_accum\_primary.vhd timing_sim\work\altmult_add\verilog.asm timing_sim\work\altmult_add\_primary.dat timing_sim\work\altmult_add\_primary.vhd timing_sim\work\altpll\verilog.asm timing_sim\work\altpll\_primary.dat timing_sim\work\altpll\_primary.vhd timing_sim\work\altqpram\verilog.asm timing_sim\work\altqpram\_primary.dat timing_sim\work\altqpram\_primary.vhd timing_sim\work\altshift_taps\verilog.asm timing_sim\work\altshift_taps\_primary.dat timing_sim\work\altshift_taps\_primary.vhd timing_sim\work\altsqrt\verilog.asm timing_sim\work\altsqrt\_primary.dat timing_sim\work\altsqrt\_primary.vhd timing_sim\work\altsyncram\verilog.asm timing_sim\work\altsyncram\_primary.dat timing_sim\work\altsyncram\_primary.vhd timing_sim\work\alt_exc_dpram\verilog.asm timing_sim\work\alt_exc_dpram\_primary.dat timing_sim\work\alt_exc_dpram\_primary.vhd timing_sim\work\alt_exc_upcore\verilog.asm timing_sim\work\alt_exc_upcore\_primary.dat timing_sim\work\alt_exc_upcore\_primary.vhd timing_sim\work\and1\verilog.asm timing_sim\work\and1\_primary.dat timing_sim\work\and1\_primary.vhd timing_sim\work\and16\verilog.asm timing_sim\work\and16\_primary.dat timing_sim\work\and16\_primary.vhd timing_sim\work\arm_m_cntr\verilog.asm timing_sim\work\arm_m_cntr\_primary.dat timing_sim\work\arm_m_cntr\_primary.vhd timing_sim\work\arm_n_cntr\verilog.asm timing_sim\work\arm_n_cntr\_primary.dat timing_sim\work\arm_n_cntr\_primary.vhd timing_sim\work\arm_scale_cntr\verilog.asm timing_sim\work\arm_scale_cntr\_primary.dat timing_sim\work\arm_scale_cntr\_primary.vhd timing_sim\work\a_graycounter\verilog.asm timing_sim\work\a_graycounter\_primary.dat timing_sim\work\a_graycounter\_primary.vhd timing_sim\work\b17mux21\verilog.asm timing_sim\work\b17mux21\_primary.dat timing_sim\work\b17mux21\_primary.vhd timing_sim\work\b5mux21\verilog.asm timing_sim\work\b5mux21\_primary.dat timing_sim\work\b5mux21\_primary.vhd timing_sim\work\bmux21\verilog.asm timing_sim\work\bmux21\_primary.dat timing_sim\work\bmux21\_primary.vhd timing_sim\work\carry\verilog.asm timing_sim\work\carry\_primary.dat timing_sim\work\carry\_primary.vhd timing_sim\work\carry_sum\verilog.asm timing_sim\work\carry_sum\_primary.dat timing_sim\work\carry_sum\_primary.vhd timing_sim\work\cascade\verilog.asm timing_sim\work\cascade\_primary.dat timing_sim\work\cascade\_primary.vhd timing_sim\work\dcfifo\verilog.asm timing_sim\work\dcfifo\_primary.dat timing_sim\work\dcfifo\_primary.vhd timing_sim\work\dcfifo_async\verilog.asm timing_sim\work\dcfifo_async\_primary.dat timing_sim\work\dcfifo_async\_primary.vhd timing_sim\work\dcfifo_dffpipe\verilog.asm timing_sim\work\dcfifo_dffpipe\_primary.dat timing_sim\work\dcfifo_dffpipe\_primary.vhd timing_sim\work\dcfifo_fefifo\verilog.asm timing_sim\work\dcfifo_fefifo\_primary.dat timing_sim\work\dcfifo_fefifo\_primary.vhd timing_sim\work\dcfifo_sync\verilog.asm timing_sim\work\dcfifo_sync\_primary.dat timing_sim\work\dcfifo_sync\_primary.vhd timing_sim\work\dffe\verilog.asm timing_sim\work\dffe\_primary.dat timing_sim\work\dffe\_primary.vhd timing_sim\work\dffp\verilog.asm timing_sim\work\dffp\_primary.dat timing_sim\work\dffp\_primary.vhd timing_sim\work\exp\verilog.asm timing_sim\work\exp\_primary.dat timing_sim\work\exp\_primary.vhd timing_sim\work\global\verilog.asm timing_sim\work\global\_primary.dat timing_sim\work\global\_primary.vhd timing_sim\work\hcstratix_asynch_io\verilog.asm timing_sim\work\hcstratix_asynch_io\_primary.dat timing_sim\work\hcstratix_asynch_io\_primary.vhd timing_sim\work\hcstratix_asynch_lcell\verilog.asm timing_sim\work\hcstratix_asynch_lcell\_primary.dat timing_sim\work\hcstratix_asynch_lcell\_primary.vhd timing_sim\work\hcstratix_crcblock\verilog.asm timing_sim\work\hcstratix_crcblock\_primary.dat timing_sim\work\hcstratix_crcblock\_primary.vhd timing_sim\work\hcstratix_dll\verilog.asm timing_sim\work\hcstratix_dll\_primary.dat timing_sim\work\hcstratix_dll\_primary.vhd timing_sim\work\hcstratix_io\verilog.asm timing_sim\work\hcstratix_io\_primary.dat timing_sim\work\hcstratix_io\_primary.vhd timing_sim\work\hcstratix_io_register\verilog.asm timing_sim\work\hcstratix_io_register\_primary.dat timing_sim\work\hcstratix_io_register\_primary.vhd timing_sim\work\hcstratix_jtag\verilog.asm timing_sim\work\hcstratix_jtag\_primary.dat timing_sim\work\hcstratix_jtag\_primary.vhd timing_sim\work\hcstratix_lcell\verilog.asm timing_sim\work\hcstratix_lcell\_primary.dat timing_sim\work\hcstratix_lcell\_primary.vhd timing_sim\work\hcstratix_lcell_register\verilog.asm timing_sim\work\hcstratix_lcell_register\_primary.dat timing_sim\work\hcstratix_lcell_register\_primary.vhd timing_sim\work\hcstratix_lvds_receiver\verilog.asm timing_sim\work\hcstratix_lvds_receiver\_primary.dat timing_sim\work\hcstratix_lvds_receiver\_primary.vhd timing_sim\work\hcstratix_lvds_rx_parallel_register\verilog.asm timing_sim\work\hcstratix_lvds_rx_parallel_register\_primary.dat timing_sim\work\hcstratix_lvds_rx_parallel_register\_primary.vhd timing_sim\work\hcstratix_lvds_transmitter\verilog.asm timing_sim\work\hcstratix_lvds_transmitter\_primary.dat timing_sim\work\hcstratix_lvds_transmitter\_primary.vhd timing_sim\work\hcstratix_lvds_tx_out_block\verilog.asm timing_sim\work\hcstratix_lvds_tx_out_block\_primary.dat timing_sim\work\hcstratix_lvds_tx_out_block\_primary.vhd timing_sim\work\hcstratix_lvds_tx_parallel_register\verilog.asm timing_sim\work\hcstratix_lvds_tx_parallel_register\_primary.dat timing_sim\work\hcstratix_lvds_tx_parallel_register\_primary.vhd timing_sim\work\hcstratix_mac_mult\verilog.asm timing_sim\work\hcstratix_mac_mult\_primary.dat timing_sim\work\hcstratix_mac_mult\_primary.vhd timing_sim\work\hcstratix_mac_mult_internal\verilog.asm timing_sim\work\hcstratix_mac_mult_internal\_primary.dat timing_sim\work\hcstratix_mac_mult_internal\_primary.vhd timing_sim\work\hcstratix_mac_out\verilog.asm timing_sim\work\hcstratix_mac_out\_primary.dat timing_sim\work\hcstratix_mac_out\_primary.vhd timing_sim\work\hcstratix_mac_out_internal\verilog.asm timing_sim\work\hcstratix_mac_out_internal\_primary.dat timing_sim\work\hcstratix_mac_out_internal\_primary.vhd timing_sim\work\hcstratix_mac_register\verilog.asm timing_sim\work\hcstratix_mac_register\_primary.dat timing_sim\work\hcstratix_mac_register\_primary.vhd timing_sim\work\hcstratix_pll\verilog.asm timing_sim\work\hcstratix_pll\_primary.dat timing_sim\work\hcstratix_pll\_primary.vhd timing_sim\work\hcstratix_ram_block\verilog.asm timing_sim\work\hcstratix_ram_block\_primary.dat timing_sim\work\hcstratix_ram_block\_primary.vhd timing_sim\work\hcstratix_ram_clear\verilog.asm timing_sim\work\hcstratix_ram_clear\_primary.dat timing_sim\work\hcstratix_ram_clear\_primary.vhd timing_sim\work\hcstratix_ram_internal\verilog.asm timing_sim\work\hcstratix_ram_internal\_primary.dat timing_sim\work\hcstratix_ram_internal\_primary.vhd timing_sim\work\hcstratix_ram_register\verilog.asm timing_sim\work\hcstratix_ram_register\_primary.dat timing_sim\work\hcstratix_ram_register\_primary.vhd timing_sim\work\hcstratix_rublock\verilog.asm timing_sim\work\hcstratix_rublock\_primary.dat timing_sim\work\hcstratix_rublock\_primary.vhd timing_sim\work\hssi_fifo\verilog.asm timing_sim\work\hssi_fifo\_primary.dat timing_sim\work\hssi_fifo\_primary.vhd timing_sim\work\hssi_pll\verilog.asm timing_sim\work\hssi_pll\_primary.dat timing_sim\work\hssi_pll\_primary.vhd timing_sim\work\hssi_rx\verilog.asm timing_sim\work\hssi_rx\_primary.dat timing_sim\work\hssi_rx\_primary.vhd timing_sim\work\hssi_tx\verilog.asm timing_sim\work\hssi_tx\_primary.dat timing_sim\work\hssi_tx\_primary.vhd timing_sim\work\io_buf_opdrn\verilog.asm timing_sim\work\io_buf_opdrn\_primary.dat timing_sim\work\io_buf_opdrn\_primary.vhd timing_sim\work\io_buf_tri\verilog.asm timing_sim\work\io_buf_tri\_primary.dat timing_sim\work\io_buf_tri\_primary.vhd timing_sim\work\latch\verilog.asm timing_sim\work\latch\_primary.dat timing_sim\work\latch\_primary.vhd timing_sim\work\lcell\verilog.asm timing_sim\work\lcell\_primary.dat timing_sim\work\lcell\_primary.vhd timing_sim\work\lpm_abs\verilog.asm timing_sim\work\lpm_abs\_primary.dat timing_sim\work\lpm_abs\_primary.vhd timing_sim\work\lpm_add_sub\verilog.asm timing_sim\work\lpm_add_sub\_primary.dat timing_sim\work\lpm_add_sub\_primary.vhd timing_sim\work\lpm_and\verilog.asm timing_sim\work\lpm_and\_primary.dat timing_sim\work\lpm_and\_primary.vhd timing_sim\work\lpm_bipad\verilog.asm timing_sim\work\lpm_bipad\_primary.dat timing_sim\work\lpm_bipad\_primary.vhd timing_sim\work\lpm_bustri\verilog.asm timing_sim\work\lpm_bustri\_primary.dat timing_sim\work\lpm_bustri\_primary.vhd timing_sim\work\lpm_clshift\verilog.asm timing_sim\work\lpm_clshift\_primary.dat timing_sim\work\lpm_clshift\_primary.vhd timing_sim\work\lpm_compare\verilog.asm timing_sim\work\lpm_compare\_primary.dat timing_sim\work\lpm_compare\_primary.vhd timing_sim\work\lpm_constant\verilog.asm timing_sim\work\lpm_constant\_primary.dat timing_sim\work\lpm_constant\_primary.vhd timing_sim\work\lpm_counter\verilog.asm timing_sim\work\lpm_counter\_primary.dat timing_sim\work\lpm_counter\_primary.vhd timing_sim\work\lpm_decode\verilog.asm timing_sim\work\lpm_decode\_primary.dat timing_sim\work\lpm_decode\_primary.vhd timing_sim\work\lpm_divide\verilog.asm timing_sim\work\lpm_divide\_primary.dat timing_sim\work\lpm_divide\_primary.vhd timing_sim\work\lpm_ff\verilog.asm timing_sim\work\lpm_ff\_primary.dat timing_sim\work\lpm_ff\_primary.vhd timing_sim\work\lpm_fifo\verilog.asm timing_sim\work\lpm_fifo\_primary.dat timing_sim\work\lpm_fifo\_primary.vhd timing_sim\work\lpm_fifo_dc\verilog.asm timing_sim\work\lpm_fifo_dc\_primary.dat timing_sim\work\lpm_fifo_dc\_primary.vhd timing_sim\work\lpm_fifo_dc_async\verilog.asm timing_sim\work\lpm_fifo_dc_async\_primary.dat timing_sim\work\lpm_fifo_dc_async\_primary.vhd timing_sim\work\lpm_fifo_dc_dffpipe\verilog.asm timing_sim\work\lpm_fifo_dc_dffpipe\_primary.dat timing_sim\work\lpm_fifo_dc_dffpipe\_primary.vhd timing_sim\work\lpm_fifo_dc_fefifo\verilog.asm timing_sim\work\lpm_fifo_dc_fefifo\_primary.dat timing_sim\work\lpm_fifo_dc_fefifo\_primary.vhd timing_sim\work\lpm_inpad\verilog.asm timing_sim\work\lpm_inpad\_primary.dat timing_sim\work\lpm_inpad\_primary.vhd timing_sim\work\lpm_inv\verilog.asm timing_sim\work\lpm_inv\_primary.dat timing_sim\work\lpm_inv\_primary.vhd timing_sim\work\lpm_latch\verilog.asm timing_sim\work\lpm_latch\_primary.dat timing_sim\work\lpm_latch\_primary.vhd timing_sim\work\lpm_mult\verilog.asm timing_sim\work\lpm_mult\_primary.dat timing_sim\work\lpm_mult\_primary.vhd timing_sim\work\lpm_mux\verilog.asm timing_sim\work\lpm_mux\_primary.dat timing_sim\work\lpm_mux\_primary.vhd timing_sim\work\lpm_or\verilog.asm timing_sim\work\lpm_or\_primary.dat timing_sim\work\lpm_or\_primary.vhd timing_sim\work\lpm_outpad\verilog.asm timing_sim\work\lpm_outpad\_primary.dat timing_sim\work\lpm_outpad\_primary.vhd timing_sim\work\lpm_ram_dp\verilog.asm timing_sim\work\lpm_ram_dp\_primary.dat timing_sim\work\lpm_ram_dp\_primary.vhd timing_sim\work\lpm_ram_dq\verilog.asm timing_sim\work\lpm_ram_dq\_primary.dat timing_sim\work\lpm_ram_dq\_primary.vhd timing_sim\work\lpm_ram_io\verilog.asm timing_sim\work\lpm_ram_io\_primary.dat timing_sim\work\lpm_ram_io\_primary.vhd timing_sim\work\lpm_rom\verilog.asm timing_sim\work\lpm_rom\_primary.dat timing_sim\work\lpm_rom\_primary.vhd timing_sim\work\lpm_shiftreg\verilog.asm timing_sim\work\lpm_shiftreg\_primary.dat timing_sim\work\lpm_shiftreg\_primary.vhd timing_sim\work\lpm_xor\verilog.asm timing_sim\work\lpm_xor\_primary.dat timing_sim\work\lpm_xor\_primary.vhd timing_sim\work\mux21\verilog.asm timing_sim\work\mux21\_primary.dat timing_sim\work\mux21\_primary.vhd timing_sim\work\mux41\verilog.asm timing_sim\work\mux41\_primary.dat timing_sim\work\mux41\_primary.vhd timing_sim\work\m_cntr\verilog.asm timing_sim\work\m_cntr\_primary.dat timing_sim\work\m_cntr\_primary.vhd timing_sim\work\nmux21\verilog.asm timing_sim\work\nmux21\_primary.dat timing_sim\work\nmux21\_primary.vhd timing_sim\work\n_cntr\verilog.asm timing_sim\work\n_cntr\_primary.dat timing_sim\work\n_cntr\_primary.vhd timing_sim\work\oper_add\verilog.asm timing_sim\work\oper_add\_primary.dat timing_sim\work\oper_add\_primary.vhd timing_sim\work\oper_addsub\verilog.asm timing_sim\work\oper_addsub\_primary.dat timing_sim\work\oper_addsub\_primary.vhd timing_sim\work\oper_bus_mux\verilog.asm timing_sim\work\oper_bus_mux\_primary.dat timing_sim\work\oper_bus_mux\_primary.vhd timing_sim\work\oper_decoder\verilog.asm timing_sim\work\oper_decoder\_primary.dat timing_sim\work\oper_decoder\_primary.vhd timing_sim\work\oper_div\verilog.asm timing_sim\work\oper_div\_primary.dat timing_sim\work\oper_div\_primary.vhd timing_sim\work\oper_left_shift\verilog.asm timing_sim\work\oper_left_shift\_primary.dat timing_sim\work\oper_left_shift\_primary.vhd timing_sim\work\oper_less_than\verilog.asm timing_sim\work\oper_less_than\_primary.dat timing_sim\work\oper_less_than\_primary.vhd timing_sim\work\oper_mod\verilog.asm timing_sim\work\oper_mod\_primary.dat timing_sim\work\oper_mod\_primary.vhd timing_sim\work\oper_mult\verilog.asm timing_sim\work\oper_mult\_primary.dat timing_sim\work\oper_mult\_primary.vhd timing_sim\work\oper_mux\verilog.asm timing_sim\work\oper_mux\_primary.dat timing_sim\work\oper_mux\_primary.vhd timing_sim\work\oper_right_shift\verilog.asm timing_sim\work\oper_right_shift\_primary.dat timing_sim\work\oper_right_shift\_primary.vhd timing_sim\work\oper_rotate_left\verilog.asm timing_sim\work\oper_rotate_left\_primary.dat timing_sim\work\oper_rotate_left\_primary.vhd timing_sim\work\oper_rotate_right\verilog.asm timing_sim\work\oper_rotate_right\_primary.dat timing_sim\work\oper_rotate_right\_primary.vhd timing_sim\work\oper_selector\verilog.asm timing_sim\work\oper_selector\_primary.dat timing_sim\work\oper_selector\_primary.vhd timing_sim\work\parallel_add\verilog.asm timing_sim\work\parallel_add\_primary.dat timing_sim\work\parallel_add\_primary.vhd timing_sim\work\pll_ram\verilog.asm timing_sim\work\pll_ram\_primary.dat timing_sim\work\pll_ram\_primary.vhd timing_sim\work\pll_ram_tb\verilog.asm timing_sim\work\pll_ram_tb\_primary.dat timing_sim\work\pll_ram_tb\_primary.vhd timing_sim\work\pll_reg\verilog.asm timing_sim\work\pll_reg\_primary.dat timing_sim\work\pll_reg\_primary.vhd timing_sim\work\scale_cntr\verilog.asm timing_sim\work\scale_cntr\_primary.dat timing_sim\work\scale_cntr\_primary.vhd timing_sim\work\scfifo\verilog.asm timing_sim\work\scfifo\_primary.dat timing_sim\work\scfifo\_primary.vhd timing_sim\work\stratixgx_dpa_lvds_rx\verilog.asm timing_sim\work\stratixgx_dpa_lvds_rx\_primary.dat timing_sim\work\stratixgx_dpa_lvds_rx\_primary.vhd timing_sim\work\stratixii_lvds_rx\verilog.asm timing_sim\work\stratixii_lvds_rx\_primary.dat timing_sim\work\stratixii_lvds_rx\_primary.vhd timing_sim\work\stratixii_tx_outclk\verilog.asm timing_sim\work\stratixii_tx_outclk\_primary.dat timing_sim\work\stratixii_tx_outclk\_primary.vhd timing_sim\work\stratix_asynch_io\verilog.asm timing_sim\work\stratix_asynch_io\_primary.dat timing_sim\work\stratix_asynch_io\_primary.vhd timing_sim\work\stratix_asynch_lcell\verilog.asm timing_sim\work\stratix_asynch_lcell\_primary.dat timing_sim\work\stratix_asynch_lcell\_primary.vhd timing_sim\work\stratix_crcblock\verilog.asm timing_sim\work\stratix_crcblock\_primary.dat timing_sim\work\stratix_crcblock\_primary.vhd timing_sim\work\stratix_dll\verilog.asm timing_sim\work\stratix_dll\_primary.dat timing_sim\work\stratix_dll\_primary.vhd timing_sim\work\stratix_io\verilog.asm timing_sim\work\stratix_io\_primary.dat timing_sim\work\stratix_io\_primary.vhd timing_sim\work\stratix_io_register\verilog.asm timing_sim\work\stratix_io_register\_primary.dat timing_sim\work\stratix_io_register\_primary.vhd timing_sim\work\stratix_jtag\verilog.asm timing_sim\work\stratix_jtag\_primary.dat timing_sim\work\stratix_jtag\_primary.vhd timing_sim\work\stratix_lcell\verilog.asm timing_sim\work\stratix_lcell\_primary.dat timing_sim\work\stratix_lcell\_primary.vhd timing_sim\work\stratix_lcell_register\verilog.asm timing_sim\work\stratix_lcell_register\_primary.dat timing_sim\work\stratix_lcell_register\_primary.vhd timing_sim\work\stratix_lvds_receiver\verilog.asm timing_sim\work\stratix_lvds_receiver\_primary.dat timing_sim\work\stratix_lvds_receiver\_primary.vhd timing_sim\work\stratix_lvds_rx\verilog.asm timing_sim\work\stratix_lvds_rx\_primary.dat timing_sim\work\stratix_lvds_rx\_primary.vhd timing_sim\work\stratix_lvds_rx_parallel_register\verilog.asm timing_sim\work\stratix_lvds_rx_parallel_register\_primary.dat timing_sim\work\stratix_lvds_rx_parallel_register\_primary.vhd timing_sim\work\stratix_lvds_transmitter\verilog.asm timing_sim\work\stratix_lvds_transmitter\_primary.dat timing_sim\work\stratix_lvds_transmitter\_primary.vhd timing_sim\work\stratix_lvds_tx_out_block\verilog.asm timing_sim\work\stratix_lvds_tx_out_block\_primary.dat timing_sim\work\stratix_lvds_tx_out_block\_primary.vhd timing_sim\work\stratix_lvds_tx_parallel_register\verilog.asm timing_sim\work\stratix_lvds_tx_parallel_register\_primary.dat timing_sim\work\stratix_lvds_tx_parallel_register\_primary.vhd timing_sim\work\stratix_mac_mult\verilog.asm timing_sim\work\stratix_mac_mult\_primary.dat timing_sim\work\stratix_mac_mult\_primary.vhd timing_sim\work\stratix_mac_mult_internal\verilog.asm timing_sim\work\stratix_mac_mult_internal\_primary.dat timing_sim\work\stratix_mac_mult_internal\_primary.vhd timing_sim\work\stratix_mac_out\verilog.asm timing_sim\work\stratix_mac_out\_primary.dat timing_sim\work\stratix_mac_out\_primary.vhd timing_sim\work\stratix_mac_out_internal\verilog.asm timing_sim\work\stratix_mac_out_internal\_primary.dat timing_sim\work\stratix_mac_out_internal\_primary.vhd timing_sim\work\stratix_mac_register\verilog.asm timing_sim\work\stratix_mac_register\_primary.dat timing_sim\work\stratix_mac_register\_primary.vhd timing_sim\work\stratix_pll\verilog.asm timing_sim\work\stratix_pll\_primary.dat timing_sim\work\stratix_pll\_primary.vhd timing_sim\work\stratix_ram_block\verilog.asm timing_sim\work\stratix_ram_block\_primary.dat timing_sim\work\stratix_ram_block\_primary.vhd timing_sim\work\stratix_ram_clear\verilog.asm timing_sim\work\stratix_ram_clear\_primary.dat timing_sim\work\stratix_ram_clear\_primary.vhd timing_sim\work\stratix_ram_internal\verilog.asm timing_sim\work\stratix_ram_internal\_primary.dat timing_sim\work\stratix_ram_internal\_primary.vhd timing_sim\work\stratix_ram_register\verilog.asm timing_sim\work\stratix_ram_register\_primary.dat timing_sim\work\stratix_ram_register\_primary.vhd timing_sim\work\stratix_rublock\verilog.asm timing_sim\work\stratix_rublock\_primary.dat timing_sim\work\stratix_rublock\_primary.vhd timing_sim\work\stx_m_cntr\verilog.asm timing_sim\work\stx_m_cntr\_primary.dat timing_sim\work\stx_m_cntr\_primary.vhd timing_sim\work\stx_n_cntr\verilog.asm timing_sim\work\stx_n_cntr\_primary.dat timing_sim\work\stx_n_cntr\_primary.vhd timing_sim\work\stx_scale_cntr\verilog.asm timing_sim\work\stx_scale_cntr\_primary.dat timing_sim\work\stx_scale_cntr\_primary.vhd timing_sim\work\tri_bus\verilog.asm timing_sim\work\tri_bus\_primary.dat timing_sim\work\tri_bus\_primary.vhd timing_sim\work\_info func_sim\work\dpram8x32 func_sim\work\pllx2 func_sim\work\pll_ram func_sim\work\pll_ram_tb pll_ram\simulation\modelsim source\post-simulation\modelsim timing_sim\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s timing_sim\work\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s timing_sim\work\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n timing_sim\work\@m@f_pll_reg timing_sim\work\@m@f_ram7x20_syn timing_sim\work\@m@f_stratixii_pll timing_sim\work\@m@f_stratix_pll timing_sim\work\@p@r@i@m_@d@f@f@e timing_sim\work\alt3pram timing_sim\work\altaccumulate timing_sim\work\altcam timing_sim\work\altcdr_rx timing_sim\work\altcdr_tx timing_sim\work\altclklock timing_sim\work\altddio_bidir timing_sim\work\altddio_in timing_sim\work\altddio_out timing_sim\work\altdpram timing_sim\work\altfp_mult timing_sim\work\altlvds_rx timing_sim\work\altlvds_tx timing_sim\work\altmult_accum timing_sim\work\altmult_add timing_sim\work\altpll timing_sim\work\altqpram timing_sim\work\altshift_taps timing_sim\work\altsqrt timing_sim\work\altsyncram timing_sim\work\alt_exc_dpram timing_sim\work\alt_exc_upcore timing_sim\work\and1 timing_sim\work\and16 timing_sim\work\arm_m_cntr timing_sim\work\arm_n_cntr timing_sim\work\arm_scale_cntr timing_sim\work\a_graycounter timing_sim\work\b17mux21 timing_sim\work\b5mux21 timing_sim\work\bmux21 timing_sim\work\carry timing_sim\work\carry_sum timing_sim\work\cascade timing_sim\work\dcfifo timing_sim\work\dcfifo_async timing_sim\work\dcfifo_dffpipe timing_sim\work\dcfifo_fefifo timing_sim\work\dcfifo_sync timing_sim\work\dffe timing_sim\work\dffp timing_sim\work\exp timing_sim\work\global timing_sim\work\hcstratix_asynch_io timing_sim\work\hcstratix_asynch_lcell timing_sim\work\hcstratix_crcblock timing_sim\work\hcstratix_dll timing_sim\work\hcstratix_io timing_sim\work\hcstratix_io_register timing_sim\work\hcstratix_jtag timing_sim\work\hcstratix_lcell timing_sim\work\hcstratix_lcell_register timing_sim\work\hcstratix_lvds_receiver timing_sim\work\hcstratix_lvds_rx_parallel_register timing_sim\work\hcstratix_lvds_transmitter timing_sim\work\hcstratix_lvds_tx_out_block timing_sim\work\hcstratix_lvds_tx_parallel_register timing_sim\work\hcstratix_mac_mult timing_sim\work\hcstratix_mac_mult_internal timing_sim\work\hcstratix_mac_out timing_sim\work\hcstratix_mac_out_internal timing_sim\work\hcstratix_mac_register timing_sim\work\hcstratix_pll timing_sim\work\hcstratix_ram_block timing_sim\work\hcstratix_ram_clear timing_sim\work\hcstratix_ram_internal timing_sim\work\hcstratix_ram_register timing_sim\work\hcstratix_rublock timing_sim\work\hssi_fifo timing_sim\work\hssi_pll timing_sim\work\hssi_rx timing_sim\work\hssi_tx timing_sim\work\io_buf_opdrn timing_sim\work\io_buf_tri timing_sim\work\latch timing_sim\work\lcell timing_sim\work\lpm_abs timing_sim\work\lpm_add_sub timing_sim\work\lpm_and timing_sim\work\lpm_bipad timing_sim\work\lpm_bustri timing_sim\work\lpm_clshift timing_sim\work\lpm_compare timing_sim\work\lpm_constant timing_sim\work\lpm_counter timing_sim\work\lpm_decode timing_sim\work\lpm_divide timing_sim\work\lpm_ff timing_sim\work\lpm_fifo timing_sim\work\lpm_fifo_dc timing_sim\work\lpm_fifo_dc_async timing_sim\work\lpm_fifo_dc_dffpipe timing_sim\work\lpm_fifo_dc_fefifo timing_sim\work\lpm_inpad timing_sim\work\lpm_inv timing_sim\work\lpm_latch timing_sim\work\lpm_mult timing_sim\work\lpm_mux timing_sim\work\lpm_or timing_sim\work\lpm_outpad timing_sim\work\lpm_ram_dp timing_sim\work\lpm_ram_dq timing_sim\work\lpm_ram_io timing_sim\work\lpm_rom timing_sim\work\lpm_shiftreg timing_sim\work\lpm_xor timing_sim\work\mux21 timing_sim\work\mux41 timing_sim\work\m_cntr timing_sim\work\nmux21 timing_sim\work\n_cntr timing_sim\work\oper_add timing_sim\work\oper_addsub timing_sim\work\oper_bus_mux timing_sim\work\oper_decoder timing_sim\work\oper_div timing_sim\work\oper_left_shift timing_sim\work\oper_less_than timing_sim\work\oper_mod timing_sim\work\oper_mult timing_sim\work\oper_mux timing_sim\work\oper_right_shift timing_sim\work\oper_rotate_left timing_sim\work\oper_rotate_right timing_sim\work\oper_selector timing_sim\work\parallel_add timing_sim\work\pll_ram timing_sim\work\pll_ram_tb timing_sim\work\pll_reg timing_sim\work\scale_cntr timing_sim\work\scfifo timing_sim\work\stratixgx_dpa_lvds_rx timing_sim\work\stratixii_lvds_rx timing_sim\work\stratixii_tx_outclk timing_sim\work\stratix_asynch_io timing_sim\work\stratix_asynch_lcell timing_sim\work\stratix_crcblock timing_sim\work\stratix_dll timing_sim\work\stratix_io timing_sim\work\stratix_io_register timing_sim\work\stratix_jtag timing_sim\work\stratix_lcell timing_sim\work\stratix_lcell_register timing_sim\work\stratix_lvds_receiver timing_sim\work\stratix_lvds_rx timing_sim\work\stratix_lvds_rx_parallel_register timing_sim\work\stratix_lvds_transmitter timing_sim\work\stratix_lvds_tx_out_block timing_sim\work\stratix_lvds_tx_parallel_register timing_sim\work\stratix_mac_mult timing_sim\work\stratix_mac_mult_internal timing_sim\work\stratix_mac_out timing_sim\work\stratix_mac_out_internal timing_sim\work\stratix_mac_register timing_sim\work\stratix_pll timing_sim\work\stratix_ram_block timing_sim\work\stratix_ram_clear timing_sim\work\stratix_ram_internal timing_sim\work\stratix_ram_register timing_sim\work\stratix_rublock timing_sim\work\stx_m_cntr timing_sim\work\stx_n_cntr timing_sim\work\stx_scale_cntr timing_sim\work\tri_bus func_sim\work pll_ram\db pll_ram\simulation source\post-simulation timing_sim\-help timing_sim\work Altera_lib_files func_sim pll_ram source timing_sim