文件名称:Example-b3-1
介绍说明－－下载内容均来自于网络，请自行研究使用
使用Quartus II设计FPGA的应用设计实例
“\Example-b3-1\uart_regs\src”目录下为设计源文件
“\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块
“\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件
“\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件
“\Example-b3-1\uart_regs\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
“\Example-b3-1\uart_regs\src”目录下为设计源文件
“\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块
“\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件
“\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件
“\Example-b3-1\uart_regs\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
相关搜索： vhdl
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下载文件列表
uart_regs
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\sim.cfg
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
.........\...\.......\uart_regs_h.vwf
.........\...\.......\uart_regs_pre.vwf
.........\...\parsim
.........\src
.........\...\sch
.........\...\...\db
.........\...\...\lpm_mux0.bsf
.........\...\...\lpm_mux0.v
.........\...\...\lpm_mux0_bb.v
.........\...\...\sch_exam.bdf
.........\...\seriesPort.v
.........\...\uart_defines.v
.........\...\uart_receiver.v
.........\...\uart_regs.v
.........\...\uart_transmitter.v
示例说明.doc
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\sim.cfg
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
.........\...\.......\uart_regs_h.vwf
.........\...\.......\uart_regs_pre.vwf
.........\...\parsim
.........\src
.........\...\sch
.........\...\...\db
.........\...\...\lpm_mux0.bsf
.........\...\...\lpm_mux0.v
.........\...\...\lpm_mux0_bb.v
.........\...\...\sch_exam.bdf
.........\...\seriesPort.v
.........\...\uart_defines.v
.........\...\uart_receiver.v
.........\...\uart_regs.v
.........\...\uart_transmitter.v
示例说明.doc