文件名称:SouceCode_0f_DDR_SDRAM_Controller_by_VHDL
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VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SouceCode_0f_DDR_SDRAM_Controller_by_VHDL
.........................................\DDR SDRAM Controller.files
.........................................\..........................\arrow.gif
.........................................\..........................\arrow1.gif
.........................................\..........................\diskette.gif
.........................................\..........................\external.css
.........................................\..........................\go.gif
.........................................\..........................\header.gif
.........................................\..........................\make_agent_emb.jpg
.........................................\..........................\pdfmid.gif
.........................................\..........................\ref_design_logo.gif
.........................................\..........................\spacer.gif
.........................................\DDR SDRAM Controller.htm
.........................................\DDR SDRAM Controller.pdf
.........................................\source
.........................................\......\ddr_ctrl.v
.........................................\......\ddr_data.v
.........................................\......\ddr_par.v
.........................................\......\ddr_pll_orca.v
.........................................\......\ddr_pll_orca_sp.v
.........................................\......\ddr_sig.v
.........................................\......\ddr_top.v
.........................................\testbench
.........................................\.........\ddr_tb.v
.........................................\.........\stimulus.v
.........................................\DDR SDRAM Controller.files
.........................................\..........................\arrow.gif
.........................................\..........................\arrow1.gif
.........................................\..........................\diskette.gif
.........................................\..........................\external.css
.........................................\..........................\go.gif
.........................................\..........................\header.gif
.........................................\..........................\make_agent_emb.jpg
.........................................\..........................\pdfmid.gif
.........................................\..........................\ref_design_logo.gif
.........................................\..........................\spacer.gif
.........................................\DDR SDRAM Controller.htm
.........................................\DDR SDRAM Controller.pdf
.........................................\source
.........................................\......\ddr_ctrl.v
.........................................\......\ddr_data.v
.........................................\......\ddr_par.v
.........................................\......\ddr_pll_orca.v
.........................................\......\ddr_pll_orca_sp.v
.........................................\......\ddr_sig.v
.........................................\......\ddr_top.v
.........................................\testbench
.........................................\.........\ddr_tb.v
.........................................\.........\stimulus.v