文件名称:ddr_ctrlv
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ddr ram controller vhdl code
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下载文件列表
压缩包 : 31767677ddr_ctrlv.rar 列表 ddr_ctrlv\.bzrignore ddr_ctrlv\bench\fml_memtest.v ddr_ctrlv\bench\lac\dp_ram.v ddr_ctrlv\bench\lac\lac.v ddr_ctrlv\bench\lac\uart.v ddr_ctrlv\bench\lac ddr_ctrlv\bench\system.v ddr_ctrlv\bench ddr_ctrlv\rtl\ddr_clkgen.v ddr_ctrlv\rtl\ddr_ctrl.v ddr_ctrlv\rtl\ddr_include.v ddr_ctrlv\rtl\ddr_init.v ddr_ctrlv\rtl\ddr_pulse78.v ddr_ctrlv\rtl\ddr_rpath.v ddr_ctrlv\rtl\ddr_wpath.v ddr_ctrlv\rtl\gray_counter.v ddr_ctrlv\rtl\rotary.v ddr_ctrlv\rtl\async_fifo.v.bak ddr_ctrlv\rtl\async_fifo.v ddr_ctrlv\rtl ddr_ctrlv\sim\ddr\ddr.v ddr_ctrlv\sim\ddr\parameters.v ddr_ctrlv\sim\ddr\readme.txt ddr_ctrlv\sim\ddr ddr_ctrlv\sim\Makefile ddr_ctrlv\sim\system_tb.list ddr_ctrlv\sim\system_tb.save ddr_ctrlv\sim\system_tb.v ddr_ctrlv\sim\unisims\BUFG.v ddr_ctrlv\sim\unisims\DCM_SP.v ddr_ctrlv\sim\unisims\FDDRRSE.v ddr_ctrlv\sim\unisims ddr_ctrlv\sim ddr_ctrlv\syn\Makefile ddr_ctrlv\syn\system.prj ddr_ctrlv\syn\system.ucf ddr_ctrlv\syn\system.xst ddr_ctrlv\syn ddr_ctrlv