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[VHDL编程] bingchuan2
说明:verilogHDL编写的并串转换模块,在ISE软件中仿真过,可综合,绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct<李晶> 在 2024-11-20 上传 | 大小:208kb | 下载:0
[VHDL编程] modulation
说明:verilogHDL编写的QPSK选相法调制模块,在ISE软件中仿真过,可综合,绝对是正确的-verilogHDL preparation phase of the QPSK modulation selection module, in the ISE simulation software that can be integrated, is absolutely correct<李晶> 在 2024-11-20 上传 | 大小:4.74mb | 下载:0
[VHDL编程] Codingexperimentcrcdcord
说明:编码实验Your use of Altera Corporation s design tools, logic functions and other software and tools, and its AMPP partner logic -Coding experiment<吕旭> 在 2024-11-20 上传 | 大小:132kb | 下载:0