说明:The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1
Boards and provides an interface for audio input and outpu <gasha> 在 2024-10-13 上传
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说明:用VHDL写的带有小时,分钟,秒的电子钟,已在FPGA开发板上调试运行过,显示very well!-Written in VHDL, with the hours, minutes, seconds, the electronic clock has been running in the FPGA development board debugger before, show very well! <赵静> 在 2024-10-13 上传
| 大小:1024 | 下载:0
说明:从0到14的计数,当然你改动下源程序,计数范围可以扩大。还带有清零的功能!-From 0 to 14 counts, of course, you change the next source, counts could be expanded. Also with the Clear function! <李海> 在 2024-10-13 上传
| 大小:1024 | 下载:0
说明:有限状态机源码,verilog语言编写。非常详细的示范了FSM状态机的编写。-Finite state machine source code, verilog language. A very detailed model of the FSM state machine preparation. <王先生> 在 2024-10-13 上传
| 大小:1024 | 下载:0