资源列表
[VHDL编程] cnt_up_down
说明:It s a counter which count to up, when on the all positions are "1", it count to down<gegry> 在 2024-11-18 上传 | 大小:1kb | 下载:0
[VHDL编程] lcd_timing_controller
说明:DE2-70 ltm timing Controller<asdasdsd> 在 2024-11-18 上传 | 大小:1kb | 下载:0
[VHDL编程] uart_receiver
说明:This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.<bhagwan> 在 2024-11-18 上传 | 大小:1kb | 下载:0
[VHDL编程] uart_transmitter
说明:This UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.<bhagwan> 在 2024-11-18 上传 | 大小:1kb | 下载:0