资源列表
[VHDL编程] XillinxFor_CKJH
说明:程控交换机芯片用的VHDL语言程序, 与DSP配合完成程控交换机功能-VHDL code for tele-communication switcher in education<alanwater> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] myself_uart_vhdl
说明:自己写的,对串口的VHDL描述,有完整testbench,特别是详细的功能说明和注释。-Wrote it myself, on the serial port of the VHDL descr iption of a complete testbench, in particular, detailed functional descr iptions and notes.<崔易> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] miniuart.tar
说明:Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication<eldis> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] quartus2-crack
说明:modelsim注册license解码解码-ModelSim license decoder decoding Register<王永> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] x2uart-all
说明:适用异步收发器设计的vhdl语言,是学习UART知识的好例程-Asynchronous Receiver Transmitter apply VHDL design language, are a good knowledge of study UART routines<xzq> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] boothmultiplier
说明:verilog code for 8-bit signed integers....its working<chaitu> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] ADC_INTERFACE
说明:it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and<yasir ateeq> 在 2025-02-04 上传 | 大小:6kb | 下载:0
[VHDL编程] C8051F040basedGPSnavigatorsimplesourcecode
说明:基于C8051F040简易GPS导航仪源代码-C8051F040-based GPS navigator simple source code<zhe> 在 2025-02-04 上传 | 大小:6kb | 下载:0