资源列表
[VHDL编程] pipeline_streamlined_divider
说明:pipeline_streamlined_divider, 一个流水线的除法器,使用Verilog HDL语言编写-pipeline_streamlined_divider, a divider using pipeline technology in verilog HDL language<谷雨> 在 2025-02-05 上传 | 大小:3kb | 下载:0
[VHDL编程] Temperature
说明:FPGA 用Verilog语言时序实现与DS18B20温度传感器读写,并把温度通过LCD来显示-FPGA with Verilog language implementation and timing DS18B20 temperature sensors to read and write, and the temperature displayed by LCD<罗永伙> 在 2025-02-05 上传 | 大小:3kb | 下载:0
[VHDL编程] Binary_search_algorithm
说明:fpga implementation of binary search algorithm using verilog code<karthick> 在 2025-02-05 上传 | 大小:3kb | 下载:0
[VHDL编程] EXAMPLES-ON-SYSTEM-VERILOG.tar
说明:THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)-THIS FILE CONTAINS AROUND 20 USEFUL EXAMPLES ON SYSTEM VERILOG (MEMORY-ARRAYS,LOGICS,DATATYPES ETC.)<ladu> 在 2025-02-05 上传 | 大小:3kb | 下载:0
[VHDL编程] log_generator
说明:log10 generator in vhdl. simulated in Modelsim<Adnan> 在 2025-02-05 上传 | 大小:3kb | 下载:0