资源列表
[VHDL编程] generator.new
说明:AVR DDS Generator. It designed for AtMega16 or similar. It can generate Sinus, Saw, Square and triangle.<Martin Valensky> 在 2025-03-16 上传 | 大小:227kb | 下载:0
[VHDL编程] uart_fpga4fun
说明:rs232通信代码,在自己的xilinx开发板上已验证通过-rs232 code with verilog has been verified<许磊> 在 2025-03-16 上传 | 大小:227kb | 下载:0
[VHDL编程] mangxinhao
说明:关于盲信号的一片很好的文章,可供初入门的同学参考。-blind signal<by> 在 2025-03-16 上传 | 大小:227kb | 下载:0
[VHDL编程] zobrazenie_16_bit_cisla_paralel
说明:16 bit switch input view in hexa format on 7seg display<vylo> 在 2025-03-16 上传 | 大小:227kb | 下载:0
[VHDL编程] digitalclock
说明:digital alarm clock on lcd- written in verilog to program fpga or cpld<mary> 在 2025-03-16 上传 | 大小:227kb | 下载:0
[VHDL编程] m-sequence_gen
说明:m序列生成verilog代码,经过仿真测试,绝对可用,带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation<zyy> 在 2025-03-16 上传 | 大小:227kb | 下载:0
[VHDL编程] snake
说明:Gradient Vector Flow (GVF) snake is one kind of active contours - curves that can move within images to find the boundaries of objects. 3D active contours are also known as deformable models. GVF snake begins with calcul<jeffsantana > 在 2025-03-16 上传 | 大小:227kb | 下载:0