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[VHDL编程] FSK_modulation_VHDL
说明:FSK调制的VHDL程序,有详细注释,并在最后附上仿真图,方便理解和验证。-FSK modulation of the VHDL program, detailed annotations, and attach a simulation of the final map, to facilitate understanding and validation.<kuaile> 在 2025-03-06 上传 | 大小:30kb | 下载:0
[VHDL编程] DINAMICALLY_PROGRAMMABLE_CACHE
说明:dynamically programmable cache memory for image processing applications<Oor> 在 2025-03-06 上传 | 大小:30kb | 下载:0
[VHDL编程] Verilogexample
说明:verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statement<vkiy> 在 2025-03-06 上传 | 大小:30kb | 下载:0
[VHDL编程] sdram_controller_latest.tar
说明:sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_cont<Andrei> 在 2025-03-06 上传 | 大小:30kb | 下载:0
[VHDL编程] ARM_Instruction_Set
说明:Arm Instruction set document<immanuel> 在 2025-03-06 上传 | 大小:30kb | 下载:0