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[VHDL编程nai_ms22

说明:The received signal is given eye and BER simulation systems, MinkowskiMethod algorithm, STM32 all the information produced by the MP3.
<beifentuiben > 在 2024-11-13 上传 | 大小:8kb | 下载:0

[VHDL编程kipcd

说明:Calculate the maximum eigenvalue judgment matrix of AHP, Future line prediction, error analysis, Fractal dimension calculation algorithm matlab code blankets.
<beifentuiben > 在 2024-11-13 上传 | 大小:8kb | 下载:0

[VHDL编程tang_ip61

说明:The received signal is given eye and BER simulation systems, In the MATLAB image texture feature, Contains a common array signal processing algorithm.
<nengqeisui > 在 2024-11-13 上传 | 大小:8kb | 下载:0

[VHDL编程fkrbk

说明:A complete set of brothers, GPS and INS navigation program, Including compression ratio, image restoration computing uptime and peak signal to noise ratio.
<fentanhen > 在 2024-11-13 上传 | 大小:8kb | 下载:0

[VHDL编程iedcb

说明:SNR largest independent component analysis algorithm, Accuracy can reach 98%, Using MATLAB dynamic clustering or iterative self-organizing data analysis.
<fentanhen > 在 2024-11-13 上传 | 大小:8kb | 下载:0

[VHDL编程26_sdram_ov5640_vga_gray

说明:完成图像的实时采集与vga显示功能,摄像头为ov7670系列,开发板为黑金AX01系列(Complete the real-time image acquisition and VGA display function, the camera for the ov7670 series, the development board for the black gold AX01 series)
<凯子哥kevin > 在 2024-11-13 上传 | 大小:7.62mb | 下载:0

[VHDL编程odd_even_check

说明:用于检查数据的正确性。具体而言,在发送端,通过增加校验位,使有效数据位和校验位组成数据校验码;在接收端,根据接收的数据校验码判断数据的正确性。(For correcting the correctness of the data. Specifically, at the transmitting end, the valid data bits and the parity bits are added to the data che
<digital_wang > 在 2024-11-13 上传 | 大小:1kb | 下载:0

[VHDL编程AD9883 iic_v1.0_for_sim

说明:程序用于配置AD9883芯片寄存器,采用iic协议。 FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V
<kilyc > 在 2024-11-13 上传 | 大小:4.71mb | 下载:0

[VHDL编程original_code_multiplier

说明:16位原码乘法器,附带测试程序,实现两个16位的乘数相乘。(16-bit original code multiplier with test program)
<digital_wang > 在 2024-11-13 上传 | 大小:1kb | 下载:0

[VHDL编程unsigned_array_multiplier

说明:4X4位的无符号型阵列乘法器,可以提高乘法的运算速度(4X4 bit unsigned array multiplier, can increase the multiplication of the operation speed)
<digital_wang > 在 2024-11-13 上传 | 大小:1kb | 下载:0

[VHDL编程sequence_detector(6-state)

说明:将《Verilog数字系统设计教程》(夏宇闻)一书中第15章的源代码进行了改进,由原来的8状态精简到6状态,同样可以实现要求的功能,对于重叠出现的特定序列也可以检测到。(The source code of Chapter 15 of the Verilog Digital System Design Tutorial (Xia Yuwen) has been improved from the original 8 state to
<digital_wang > 在 2024-11-13 上传 | 大小:1kb | 下载:0

[VHDL编程MICROCHIP程序实例-debounce按键消抖

说明:MICROCHIP程序实例-debounce按键消抖(Microchip Program instance-debounce button Shake)
<zhanghongshuai > 在 2024-11-13 上传 | 大小:99kb | 下载:0
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