资源列表
[VHDL编程] pipeline_mips_simulation_using_xilinx
说明:This project is a pipeline simulator using xilinx. All of fetch, decode, execute and write back stages was implemented. That is a nice project for computer architecture course in computer engineering. Good Luck ) -Th<Fartab> 在 2025-01-20 上传 | 大小:729kb | 下载:0
[VHDL编程] digital_timer
说明:能够使用4个按键,实现调时。一个选择,一个取消,一个加时间,一个减时间。-Four keys to use to achieve the transfer. A selection, a cancel an add time, a reduced time.<lee> 在 2025-01-20 上传 | 大小:1.78mb | 下载:0
[VHDL编程] liushuideng
说明:verilog做的流水灯,分频器做半秒的tc,流水灯每半秒流动一次 -verilog do water lights, dividers do half a second tc, light water flow once every half-second<grace> 在 2025-01-20 上传 | 大小:265kb | 下载:0