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[VHDL编程qam16

说明:实现16进制的QAM调制, 编译通过-Achieve 16 to 229 QAM modulation, achieve 16 to 229 QAM modulation, compiled by
<孙靖逸> 在 2025-01-24 上传 | 大小:771kb | 下载:0

[VHDL编程alteraFPGA_RS232_communication

说明:基于alteraFPGA的RS232与电脑端的通信例程-RS232 and PC-based communication routines of alteraFPGA
<Gary> 在 2025-01-24 上传 | 大小:526kb | 下载:0

[VHDL编程alteraFPGA_SRAM_read_write_test

说明:基于alteraFPGA的SDRAM读写测试例程-Based alteraFPGA the SDRAM read and write test routines
<Gary> 在 2025-01-24 上传 | 大小:157kb | 下载:0

[VHDL编程alteraFPGA_state_machine

说明:基于alteraFPGA的有限状态机例程-Based on finite state machine routines alteraFPGA
<Gary> 在 2025-01-24 上传 | 大小:306kb | 下载:0

[VHDL编程all_cpu

说明:精简指令集CPU,可完成移位,跳转等简单功能,适用于FPGA学习,本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
<晓东> 在 2025-01-24 上传 | 大小:1.8mb | 下载:0

[VHDL编程cpu

说明:该源码为之前上传的allcpu 的仿真代码testbench,使用modsim进行仿真。-The source code for previously uploaded allcpu simulation code testbench, use modsim simulation.
<晓东> 在 2025-01-24 上传 | 大小:226kb | 下载:0

[VHDL编程i2c_verilog

说明:I2C Master IP 核 I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication
<qingmingyang> 在 2025-01-24 上传 | 大小:11kb | 下载:0

[VHDL编程fast_fpga_code

说明:ELM算法实现分类,利用VHDL语言在FPGA开发板上实现。-Clasifaication based on Extreme Learing Machine
<李幽> 在 2025-01-24 上传 | 大小:282kb | 下载:0

[VHDL编程spi_latest.tar

说明:This IP provides specifications for the SPI (Serial Peripheral Interface) Master core. Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcon
<qingmingyang> 在 2025-01-24 上传 | 大小:2.5mb | 下载:0

[VHDL编程DE2Code

说明:智能洗衣机控制器,能够实现洗衣,漂洗和脱水等功能,通过在DE2发板模拟实现.-Smart washing machine controller, to achieve laundry, rinsing and dehydration functions, DE2 development board through simulation.
<叶健> 在 2025-01-24 上传 | 大小:1.73mb | 下载:0

[VHDL编程acs

说明:This an ACS unit which can be used in log-map algorithm as well as viterbi algorithm-This is an ACS unit which can be used in log-map algorithm as well as viterbi algorithm
<arulananthan> 在 2025-01-24 上传 | 大小:1.4mb | 下载:0

[VHDL编程recursiveconvolutional

说明:This simple vhdl program of RSC encoder-This is simple vhdl program of RSC encoder
<arulananthan> 在 2025-01-24 上传 | 大小:4.61mb | 下载:0
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