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[VHDL编程] USB-2.0-source-code-by-VHDL
说明:实现USB2.0,采用VHDL编写,源代码已按类分好-USB 2.0 source code by VHDL<zzz> 在 2025-02-25 上传 | 大小:201kb | 下载:0
[VHDL编程] verilog-code-for-varying-pulses
说明:The program is written in verilog. The code is written to output a sequence of pulses with a width of that of the clock. the sequence is in the order of 1,2,3,1,5 ms delay<Srinath> 在 2025-02-25 上传 | 大小:110kb | 下载:0
[VHDL编程] 5-verilog-programs
说明:the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider<Srinath> 在 2025-02-25 上传 | 大小:5kb | 下载:0