[VHDL编程] Chapter-5

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Desi
<shixiaodong> 在 2025-03-09 上传 | 大小：15kb | 下载：0

[VHDL编程] 2DPSK

说明：vhdl,Digital phase modulation is also known as phase shift keying, 2DPSK is binary differential phase shift keying, is a kind of digital phase modulation. Digital phase modulation using carrier phase change to transmit d
<乐逍遥> 在 2025-03-09 上传 | 大小：1.82mb | 下载：0

[VHDL编程] Chapter-6

说明：练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including
<shixiaodong> 在 2025-03-09 上传 | 大小：3kb | 下载：0

[VHDL编程] Chapter-7

说明：练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, inc
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[VHDL编程] Chapter-8

说明：练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including
<shixiaodong> 在 2025-03-09 上传 | 大小：328kb | 下载：0

[VHDL编程] DE2-user-Manual-(Chinese-edition)

说明：DE2板教学开发板中文用户手册,DE2板的着眼于为在数字逻辑，计算机组织和FPGA 方面的学习提供一个理想的工具。-DE2 user Manual (Chinese edition)
<googller> 在 2025-03-09 上传 | 大小：5.48mb | 下载：0

[VHDL编程] uart_verilog

说明：用verilog语言编写的UART通信，经过调试可用。-edited in verilog language
<gofee> 在 2025-03-09 上传 | 大小：9kb | 下载：0

[VHDL编程] div3

说明：实现三分频功能，占空比为50 ，可以很好的用于解决课程设计问题！-This is used for divide the frequency,and the duty cycle is 50 .
<> 在 2025-03-09 上传 | 大小：255kb | 下载：0

[VHDL编程] tut_quartus_intro_verilog

说明：为Quartus II和DE2新手准备的tutorial，Verilog版本.-Verilog edition tutorial for beginners
<googller> 在 2025-03-09 上传 | 大小：810kb | 下载：0

[VHDL编程] degree

说明：This code is use to display angles in degrees on LCD.
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[VHDL编程] vim-vhdl

说明：Vim scr ipt for vhdl coding and vidualisation. Some special features like useful syntaxis lighting included.
<> 在 2025-03-09 上传 | 大小：23kb | 下载：0

[VHDL编程] vim-verilog-generator

说明：Vim scr ipt for verilog coding and vidualisation. Some special features like useful syntaxis lighting included.
<> 在 2025-03-09 上传 | 大小：33kb | 下载：0