资源列表
[VHDL编程] cf_fft_latest.tar
说明:The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers. This FFT can perform calculations on continuous streaming data<amin> 在 2025-03-03 上传 | 大小:2.98mb | 下载:0
[VHDL编程] system05_latest.tar
说明:6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz<amin> 在 2025-03-03 上传 | 大小:29kb | 下载:0
[VHDL编程] fpu100_latest.tar
说明:This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Stan<amin> 在 2025-03-03 上传 | 大小:1.88mb | 下载:0
[VHDL编程] zorro_to_wishbone_bridge_latest.tar
说明:This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at th<amin> 在 2025-03-03 上传 | 大小:10kb | 下载:0
[VHDL编程] YCbCr2RGB_O
说明:此代码是把YUV转成RGB的Verilog程序,多谢下载-This code is to convert RGB to YUV Verilog program, thank you download<Evan Xie> 在 2025-03-03 上传 | 大小:1kb | 下载:0
[VHDL编程] AlteraFPGACPLDcoder
说明:Altera FPGA/CPLD设计(基础篇)随书代码-Altera FPGA/CPLD design (fundamental) with the code book<李磊> 在 2025-03-03 上传 | 大小:8.38mb | 下载:0
[VHDL编程] AlteraFPGACPLDcoder2
说明:Altera FPGA/CPLD设计(高级篇)随书代码-Altera FPGA/CPLD Design (Senior Posts) With the written code<boto> 在 2025-03-03 上传 | 大小:3.19mb | 下载:0
[VHDL编程] 100vhdlexamples
说明:100个VHDL例子 比较全面 非常好的学习资料-100 VHDL very good example of a more comprehensive study materials<boto> 在 2025-03-03 上传 | 大小:228kb | 下载:0