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[VHDL编程] 32-bit-carry-look-ahead-adder
说明:This file contains Verilog codes<Maf> 在 2024-11-16 上传 | 大小:11kb | 下载:0
[VHDL编程] CPU_single-(2)
说明:单周期CPU设计源码,基于Quatus II,亲测可用-Single-cycle CPU design source code, based on Quatus II, pro-test available<zjy> 在 2024-11-16 上传 | 大小:2.3mb | 下载:0
[VHDL编程] full_adder
说明:用verilog语言编写的全加器模块代码,在ISE软件环境下编译开发,希望对大家有所帮助!-With verilog language full adder module code in ISE software compiler development environment, we want to help!<黎涛> 在 2024-11-16 上传 | 大小:151kb | 下载:0
[VHDL编程] PPPdecoder
说明:decoder in vhdl A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it does the reverse of encoding, but we will begin our study of encoders and decoders with decoders becau<reza> 在 2024-11-16 上传 | 大小:1.11mb | 下载:0
[VHDL编程] spartan3E-seg-driver
说明:spartan3E seg display driver-spartan 32 seg display driver<王永刚> 在 2024-11-16 上传 | 大小:143kb | 下载:0