[VHDL编程] i2c_master_slave_core_latest.tar

说明：This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.
<Andrey> 在 2025-03-10 上传 | 大小：4.35mb | 下载：0

[VHDL编程] tiny64_latest.tar

说明：Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also diff
<Andrey> 在 2025-03-10 上传 | 大小：22kb | 下载：0

[VHDL编程] can_latest.tar

说明：Controller Area Network or CAN is a control network protocol from Bosch that has found wide use in Industrial Automation and the Automotive Industry. Most of the patents of CAN are owned by Bosch and although th
<Andrey> 在 2025-03-10 上传 | 大小：1.12mb | 下载：0

[VHDL编程] a_vhd_16550_uart_latest.tar

说明：A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses
<Andrey> 在 2025-03-10 上传 | 大小：117kb | 下载：0

[VHDL编程] usb1_funct_latest.tar

说明：USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration proces
<Andrey> 在 2025-03-10 上传 | 大小：58kb | 下载：1

[VHDL编程] Isis

说明：ISIS LCD Serial RS232
<Hatem> 在 2025-03-10 上传 | 大小：23kb | 下载：0

[VHDL编程] lect-4

说明：these slides for digital logic design
<fahad> 在 2025-03-10 上传 | 大小：905kb | 下载：0

[VHDL编程] lect-1(prt-1)

说明：slides of vhdl first chapter
<fahad> 在 2025-03-10 上传 | 大小：2.29mb | 下载：0

[VHDL编程] lect-2a[3]

说明：slides of vhdl chap no 2 -slides of vhdl chap no 2 ...
<fahad> 在 2025-03-10 上传 | 大小：1.93mb | 下载：0

[VHDL编程] EDA-fenpinqi

说明：EDA多级分频器图形设计，频器输入频率为10 MHz,输出频率为1 Hz。分频器顶层图形文件设计、例化模块图形文件设计。 -Multi-level divider graphic design, frequency input frequency of 10 MHz, the output frequency of 1 Hz. Divider top-level design of graphics files, for examp
<范骏> 在 2025-03-10 上传 | 大小：33kb | 下载：0

[VHDL编程] Asynchronous-FIFO-Design

说明：异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
<林峰> 在 2025-03-10 上传 | 大小：3kb | 下载：0

[VHDL编程] e_pro_restored

说明：2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts ana
<郭冰冰> 在 2025-03-10 上传 | 大小：4.05mb | 下载：0