[VHDL编程] filter

说明：Digital filter 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
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[VHDL编程] obnar1

说明：Digital detector (a-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
<> 在 2025-03-11 上传 | 大小：206kb | 下载：0

[VHDL编程] obnar3

说明：Digital detector (b-type) 1-st level project. Xilnx System Generator sources + verilog sources (PlanAhead project). All docs are in archive. Fully work.
<> 在 2025-03-11 上传 | 大小：187kb | 下载：0

[VHDL编程] stopwatch

说明：59.59七段数码管VHDL语言编写秒表-failed to translate
<王红阳> 在 2025-03-11 上传 | 大小：1kb | 下载：0

[VHDL编程] Chapter-1

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Desi
<shixiaodong> 在 2025-03-11 上传 | 大小：2kb | 下载：0

[VHDL编程] Chapter-2

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Desi
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[VHDL编程] Chapter-3

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Desi
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[VHDL编程] Chapter-4

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Desi
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[VHDL编程] Chapter-5

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Desi
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[VHDL编程] 2DPSK

说明：vhdl,Digital phase modulation is also known as phase shift keying, 2DPSK is binary differential phase shift keying, is a kind of digital phase modulation. Digital phase modulation using carrier phase change to transmit d
<乐逍遥> 在 2025-03-11 上传 | 大小：1.82mb | 下载：0

[VHDL编程] Chapter-6

说明：练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including
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[VHDL编程] Chapter-7

说明：练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, inc
<shixiaodong> 在 2025-03-11 上传 | 大小：7kb | 下载：0