资源列表
[VHDL编程] digit_deletion_game-rev1.0
说明:digit deletion game to be implented by verilog. This game was used in casio game before 20 years. I made it in verilog. Game rule is simple. number is generated in random and user will delete number in display out<龍 龍 > 在 2025-03-19 上传 | 大小:129kb | 下载:0
[VHDL编程] parking_lot_rev1.0
说明:This Verilog source is to monitor the count of cars in 4 floors in parking lot. monitoring method is to use sensors to count Cars to enter into or leave out. Cars number is basic number enough small to learn algorith<龍 龍 > 在 2025-03-19 上传 | 大小:85kb | 下载:0
[VHDL编程] VHDLreportoftrafficlight.wps.tar
说明:该代码通过时钟,状态循环控制及显示模块实现了对于两相邻十字路*通灯到控制,同时包含了对于两路*通灯延时启动,以及人行道情况的考虑-The code of the clock, cycle control and display module status achieved for the two adjacent intersections to control traffic lights,and includes traffic<> 在 2025-03-19 上传 | 大小:731kb | 下载:0
[VHDL编程] seg_7
说明:Altera DE系列开发板都可以参考的基于Nios ii 的数码管控制显示0-f程序-display 0-f with 7-segment display on Altera DE series board.<thomas yang> 在 2025-03-19 上传 | 大小:120kb | 下载:0
[VHDL编程] key
说明:基于Nios ii处理器的响应按键程序 -Processor-based Nios ii response key program<thomas yang> 在 2025-03-19 上传 | 大小:106kb | 下载:0
[VHDL编程] test
说明:DE1开发板基于Nios ii的10秒钟语音录放程序-DE1 development board based on Nios ii 10 seconds voice recording program<thomas yang> 在 2025-03-19 上传 | 大小:14kb | 下载:0
[VHDL编程] DE1_i2sound
说明:基于DE1的用verilog控制FPGA发声-The DE1-based sound with verilog control FPGA<thomas yang> 在 2025-03-19 上传 | 大小:627kb | 下载:0
[VHDL编程] DE1_synthesizer
说明:基于DE1开发板的verilog 响应键盘发声的声音合成器-DE1 development board based on the response to the voice synthesizer keyboard sound<thomas yang> 在 2025-03-19 上传 | 大小:3.71mb | 下载:0
[VHDL编程] DE2_NET
说明:基于nios ii处理器的net通信程序 -Nios ii processor based on the net communication program<thomas yang> 在 2025-03-19 上传 | 大小:1.74mb | 下载:0
[VHDL编程] DE2_NIOS_HOST_MOUSE_VGA
说明:基于altera FPGA开发板的鼠标VGA显示-Altera FPGA development board based on the mouse VGA display<thomas yang> 在 2025-03-19 上传 | 大小:1.79mb | 下载:0