资源列表
[VHDL编程] 8BITCONDITIONALSUMADDER
说明:it is verilog code for 8 bit conditional sum adder using veriwe-it is verilog code for 8 bit conditional sum adder using veriwell<kaleem> 在 2025-02-13 上传 | 大小:29kb | 下载:0
[VHDL编程] encoder_binary
说明:一个简单的FPGA实现的编码器,但程序中有详细的说明,并附有测试凳,可以以此为基础设计更复杂的编码器-FPGA realization of a simple encoder, but the procedure described in detail, together with a test bench, you can as a basis for designing more complex encoder<luosheng> 在 2025-02-13 上传 | 大小:405kb | 下载:0
[VHDL编程] ourdev_457422
说明:Verilog HDL教程包含大量实验例子-Verilog HDL tutorials contain a large number of experimental examples<sunnannan> 在 2025-02-13 上传 | 大小:2.79mb | 下载:0
[VHDL编程] hdbn_latest.tar
说明:This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-<chaitanya> 在 2025-02-13 上传 | 大小:195kb | 下载:0
[VHDL编程] bluespec-80211atransmitter_latest.tar
说明:This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.-This package implement<chaitanya> 在 2025-02-13 上传 | 大小:259kb | 下载:0
[VHDL编程] jiyuchuankoujishu
说明:计算机在HDL语言下实现串口技术,UART相关资料-BASIC IN HDL language,chuankou jishu<tongchao> 在 2025-02-13 上传 | 大小:301kb | 下载:0