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[VHDL编程8BITCONDITIONALSUMADDER

说明:it is verilog code for 8 bit conditional sum adder using veriwe-it is verilog code for 8 bit conditional sum adder using veriwell
<kaleem> 在 2025-02-13 上传 | 大小:29kb | 下载:0

[VHDL编程encoder_binary

说明:一个简单的FPGA实现的编码器,但程序中有详细的说明,并附有测试凳,可以以此为基础设计更复杂的编码器-FPGA realization of a simple encoder, but the procedure described in detail, together with a test bench, you can as a basis for designing more complex encoder
<luosheng> 在 2025-02-13 上传 | 大小:405kb | 下载:0

[VHDL编程FINALAB

说明:it is veri log code for ALU comparator and shift register using veriwe-it is veri log code for ALU comparator and shift register using veriwell
<kaleem> 在 2025-02-13 上传 | 大小:7kb | 下载:0

[VHDL编程finallab

说明:introduction to veri well and behaviural modeling code for 4 to 1 mux
<kaleem> 在 2025-02-13 上传 | 大小:171kb | 下载:0

[VHDL编程FPGA

说明:里面有用NIOS2与SOPC的做的一个串口程序,还有详细文档步骤,对于学习SOPC者有很大帮助-Inside useful NIOS2 to do with the SOPC a serial program, as well as detailed documentation steps, for the study were of great help to SOPC
<邓伟> 在 2025-02-13 上传 | 大小:12.66mb | 下载:0

[VHDL编程d1_dec

说明:d1(BT.656) video decoder VHDL code
<thorn> 在 2025-02-13 上传 | 大小:1kb | 下载:0

[VHDL编程ourdev_457422

说明:Verilog HDL教程包含大量实验例子-Verilog HDL tutorials contain a large number of experimental examples
<sunnannan> 在 2025-02-13 上传 | 大小:2.79mb | 下载:0

[VHDL编程hdbn_latest.tar

说明:This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-
<chaitanya> 在 2025-02-13 上传 | 大小:195kb | 下载:0

[VHDL编程bluespec-80211atransmitter_latest.tar

说明:This package implements a parameterized baseband hardware logic for an 802.11a Transmitter. This project has since been subsumed by the OFDM baseband project which can also be found on opencores.-This package implement
<chaitanya> 在 2025-02-13 上传 | 大小:259kb | 下载:0

[VHDL编程turbo

说明:turbo的VHDL代码 比较好啊 易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
<秋晨> 在 2025-02-13 上传 | 大小:150kb | 下载:0

[VHDL编程jiyuchuankoujishu

说明:计算机在HDL语言下实现串口技术,UART相关资料-BASIC IN HDL language,chuankou jishu
<tongchao> 在 2025-02-13 上传 | 大小:301kb | 下载:0

[VHDL编程GAFF

说明:伽罗华域GF(q)乘法器设计,完整的源代码。-Galois field GF (q) multiplier design, the complete source code.
<dayu1994> 在 2025-02-13 上传 | 大小:2kb | 下载:0
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