搜索资源列表
verilog_vga
- 用verilog HDL 语言写的在显示器上显示图案的源程序-with Verilog HDL language written on display in the pattern of the source
verilog_lcd
- 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source
Altera_uart_VHDL
- FPGA/CPLD应用,uart通讯VHDL原码.-FPGA / CPLD applications, UART communications VHDL source.
Altera_uart_Verilog
- FPGA/CPLD应用,uart的Verilog HDL原码-FPGA / CPLD applications, UART Verilog HDL source
wavefetch
- ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the w
CORDIC01
- CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Cpu_model
- Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
bfm
- Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
clock2001
- 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
crcDecode
- 比较完善的CRC编码VerilogHDL描述-more perfect descr iption of CRC coding VerilogHDL
PAOBIAO_V
- 带音乐功能的跑表VerilogHDL描述-music with the stopwatch Verilog HDL descr iption
MutiPipeACC
- 多通道的ACC设计VeerilogHDL描述-multi-channel design VeerilogHDL ACC Descr iption
gatediscrip
- 各种门电路模型的VerilogHDL描述-various gates model of Verilog HDL descr iption
manydecoders_V
- 各种解码译码电路模型的VerilogHDL描述-various decoder decoding circuit model of Verilog HDL descr iption
Verilogexamples
- Verilog变成100例，里面包含了Verilog编程中常见的一些例子，对于新手还是很有帮助的。-Verilog into 100 cases, they include a Verilog Programming common examples is very helpful for the novice.
8LEDverilog
- //led.v /*------------------------------------- LED显示模块：led(CLK,AF,ADDR,DATA) 功能： 显示 注意事项： 8位LED 参数： CLK:扫妙时钟输入，推荐1kHz AF:数码管输出，a～h ADDR:数码管选择位数出，0~2 DATA:显示数据输入0~9999 9999 编写人： 黄道斌 编写日期：
sram
- sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
DE2_i2sound
- DE2_i2sound.rar，大家快来下啊，做好了的IP核-DE2_i2sound.rar, everyone is breaking under ah, do a good job of the IP Core
DE2_Top
- DE2_Top.rar，做好了的IP核，大家开来下啊！-DE2_Top.rar, do a good job of the IP core, open to everyone under ah!
color_proc333
- 基于fpga的MJPEG编码,用硬件描述语言vlogic写的-they simply based on the JPEG coding, using hardware descr iption language to write the vlogic