搜索资源列表
verilogfifo
- verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
verilog_multiplier
- verilog实现16*16位乘法器，带测试文件-verilog achieve 16 * 16 multiplier, with test documents
fir_finall
- 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
verilog-som
- 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
dds-design
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
DSPuva16
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online. * * AUTHOR : Sun Yu * * HISTORY : 12/06/2002 *
8bit-cpu-of-mul-and-div
- 包含跳转，乘法，除法8位CPU以及一些基本的逻辑运算功能-includes Jump, multiplication, division eight CPU and some of the basic logic operations
adder215
- 有关于加法器的vhdl编程，是用赛灵思的fpga实现的，可以在赛灵思网站上找到更具体的说明-Adder on the vhdl program is the use of the Xilinx fpga achieve. Xilinx website can be found on more specific details of their
Project1-DDS
- 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
TC2345899
- 一个非常齐全的数字电路芯片资料库，内有将近一千个器件资料。-a very complete circuit chip digital database containing nearly 1,000 device information.
lookup_multi
- //4×4 查找表乘法器 module mult4x4(out,a,b,clk) output[7:0] out input[3:0] a,b input clk reg[7:0] out reg[1:0] firsta,firstb reg[1:0] seconda,secondb wire[3:0] outa,outb,outc,outd always @(posedge clk
Verilog_Development_Board_Sources
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Develo
V+m511
- M序列编码-M coding sequence
dpll0227
- DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
3fast_des
- 一个快速实现3des的算法，分别用vhcl和Veriloge语言进行编写，很实用-a rapidly 3des algorithm respectively vhcl Veriloge language and prepared very practical
81i_radix2_xfft1024_v3_2
- xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
sdram_verilog
- 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
traffic2
- 用verilog编的小程序,希望对需要的人有所帮助-verilog series with a small procedure, and I hope to the people in need some help
verilogled
- cpld-epm7128stc100-10驱动四位LED结果显示1234-cpld - epm7128stc100-10 drive four LED 1234 results
cpldPWM
- verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10