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videofram
- 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image fr a me buffer cards logical verilog procedures, Quartus II 5.0 Open
rs-codec(255-223)
- 这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
news5f
- Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
SPtransform
- Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
IICforsopcbuilder
- IIC控制器 for Sopc Builder-IIC controller for Sopc Builder
mod6_divide
- 用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
de_mux
- 一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
clock_2
- 时钟发生器，可以显示分，秒，小时，下到ＦＰＧＡ上验证过，功能基本正常-clock generator can demonstrate minutes and seconds, hours, the next to the FPGA tested normal function
MedianFilter33
- 3*3 中值滤波的verilog代码实现，已经调试通过！欢迎提出宝贵意见！-3 * 3 filtering to achieve the verilog code has been adopted debugging! Welcomed the valuable advice!
rs-codec-8-4
- encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder
key_prog
- 简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.-easy-to-read 4 * 4 keyboard and display program. To the preparation of other forms of keyboard scan procedures are certain guiding significance.
cupdesign
- 初学cup设计的极佳资料，详细介绍了cup设计的各个流程及各组件的设计-novice cup of excellent design, detail design of the cup and the various components of the process design
alu_32_bit
- verilog 32-bit ALU-verilog 32-bit ALU
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
SPI_verilogHDL
- 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI i
pwm_higt
- modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program
8051-core
- 8051单片机是一种应用最广泛的单片机.它的内核设计非常精简,这是用Verilog硬件描述语言写的8051单片机内核-8051 is a most widely used SCM. Its kernel design has been streamlined, This is used Verilog hardware descr iption language to write the 8051 microcontroller cor
LED_driver_IP_for_SOPC_BUILDER
- 一个数码管的驱动IP for SOPC BUILDER. 是学习SOPC的一个参考范例.-one of the driving digital IP for SOPC BUILDER. Learning is a Senate SOPC Examples examination.
26_1000
- 若干VHDL语言的源代码，我觉得应该用用仅供参考-several VHDL source code, I think that should be used for reference purposes only