搜索资源列表
ImageTour1
- 实现几个图片合成成一个gif，并且在每一帧上加水印-synthesize several picture into a gif file, and watermark is added to each fr a me picture.
frequence
- VHDL频率合成器，能合成十多个频率。希望对大家有用-VHDL Synthesis, can synthesize more than 10 frequencies. We hope to useful
tapestrea
- TAPESTREA is ongoing research project investigating new ways and tools to analyze, transform, and synthesize sound. This is a very experimental audio software.
语音合成-yxifu
- 编译环境：vc++.net2003 名称：语音合成软件 作者：yxifu-Program environment: VC++.net2003 Name: program of speech synthesize Programer: yxifu
武钢MIS30系统的操作说明new
- TD-PSOLA MATLAB编写语音合成模拟程序-TD-PSOLA MATLAB simulator program for speech synthesize.
Senfore_DragDrop_v4.1
- Drag and Drop Component Suite Version 4.1 Field test 5, released 16-dec-2001 ?1997-2001 Angus Johnson & Anders Melander http://www.melander.dk/delphi/dragdrop/ ------------------------------------------- Table of Co
synthesis
- 遗传算法用于微波网络综合- The heredity algorithm uses in the microwave network to synthesize
语音合成-yxifu
- 编译环境：vc++.net2003 名称：语音合成软件 作者：yxifu-Program environment: VC++.net2003 Name: program of speech synthesize Programer: yxifu
武钢MIS30系统的操作说明new
- TD-PSOLA MATLAB编写语音合成模拟程序-TD-PSOLA MATLAB simulator program for speech synthesize.
ImageTour1
- 实现几个图片合成成一个gif，并且在每一帧上加水印-synthesize several picture into a gif file, and watermark is added to each fr a me picture.
frequence
- VHDL频率合成器，能合成十多个频率。希望对大家有用-VHDL Synthesis, can synthesize more than 10 frequencies. We hope to useful
tapestrea
- TAPESTREA is ongoing research project investigating new ways and tools to analyze, transform, and synthesize sound. This is a very experimental audio software.
VERILOGHDL
- this a book about the verilog-hdl design and circuit simulation and synthesize example
smurf-0.52.6.tar
- A GTK sound font editor. Sound font files are used to synthesize instruments from audio samples for use in composing music with wavetable sound cards or software emulation. Smurf currently has AWE 32/64 and SB Live suppo
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which da
traffic_controller
- it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code writt
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state mac
Synthesize
- 我们团队一起合作利用VC做的叠前反演程序，里面包括了SGY数据读取子波建立正演模型等模块-Work together to use our team to do the VC prestack inversion procedure, which includes data read SGY wavelet speech model is set up module
Resynth
- re synthesize the speech signal