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full_add
- 一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.
399
- 用VHDL编写的8位全加器,数字分频器等程序-VHDL prepared by the eight All-Canadian, digital dividers procedures
add_1p
- 2级流水线实现的8位全加器的VHDL代码，适用于altera系列的FPGA/CPLD
add_ff8cin
- 触发器实现的，8位全加器的VHDL语言实现，适用于altera系列的FPGA
full_add
- 一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment.
399
- 用VHDL编写的8位全加器,数字分频器等程序-VHDL prepared by the eight All-Canadian, digital dividers procedures
add_1p
- 2级流水线实现的8位全加器的VHDL代码，适用于altera系列的FPGA/CPLD-Realize two lines of eight full adder of the VHDL code, applicable to altera series of FPGA/CPLD
add_ff8cin
- 触发器实现的，8位全加器的VHDL语言实现，适用于altera系列的FPGA-Flip-flop to achieve, eight full adder realize the VHDL language, applicable to altera series FPGA
Quartus7.2
- 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
add_eight
- 用VHDL写的一个8位全加器的实验程序,供新手参考-Use VHDL to write an 8-bit full adder of the experimental procedures
binary_to_decima
- 8位全加器的VHDL描述，可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL descr iption，MAX+ plus Ⅱ can be used to run test
8WEIQUANJIAQI
- 8位全加器的VHDL语言描述，有需要的顶一下。-8-bit full adder described in the VHDL language, there is a need to click the top.
hadder
- 这是一个8位全加器，利用vhdl完成了电路的构成，-this is a 8 bit adder,
quanjiaqi
- 4 级流水方式的8 位全加器-Way flow of 4 full adder 8. . . . . .
sy4
- 用VHDL语言设计了一个8位2进制全加器-VHDL language design with an 8-bit binary full adder 2
8-ADDER-VHDL
- 用硬件描述语言编写的8位全加器代码，很实用！-Using hardware descr iption language preparation 8 bits QuanJia implement code, very useful!!
VHDL-8-wei-quan-jia-qi
- 原理图输入法实现8位全加器，内含vhd源码文件和一份word介绍文件，管脚配置已经完成，芯片为EPIK30TCI443-Schematic entry method 8-bit full adder, and a source code file containing the vhd file word descr iption, pin configuration has been completed, the chip is EPI
xor8b
- 实现8位全加器，为初学者提供参考，对VHDL语言有一定了解(It's a addler of 8 bits,which is designed for new learners)
add8
- 8*8位全加器的代码 verilog语言，包含测试文件(8*8-bit full adder code verilog)
exp01_adc32
- 通过4位加法器实现32位加法器，使用串行进位的方式首先设计一个8位全加器，然后在8位全加器的基础上设计实现32位全加器(A 32 bit adder is implemented through a 4 bit adder. First, a 8 bit full adder is designed using serial carry. Then, a 32 bit full adder is designed on the basi