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用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
multi4
- fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
myproject
- 四位全加器，VHDL语言，max+plusII平台做的
用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
jiafaqi
- 实现四位加法器的VHDL代码，里面含有全加器的代码-achieve four Adder VHDL code, which contains the full adder code
multi4
- fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
myproject
- 四位全加器，VHDL语言，max+plusII平台做的-Four full-adder, VHDL language, max+ PlusII platform to do
FullAdder_4
- 这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。-This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder.
fadder4
- VHDL实现四位全加器，适合初学者，源程序下载-VHDL realization of four full adder, suitable for beginners, the source code download
VHDL_add_4
- 本程序完成带进位输入输出的四位二进制加法运算，编程思想采用真值表转换成布尔方程式，利用循环语句将一位全加器编为四位加法器。-This procedure is completed into the four-bit input and output binary adder computing, programming thinking of using truth table into a Boolean equation using
VHDLsiweiquanjiaqqi
- 这是一个利用MAX PULL 制作的VHDL的四位全加器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL using VHDL produced four full-adder process simulation map, if necessary please contact me call station
ADDER4B
- 此程序是用VHDL硬件描述语言编写的,实现四位全加器的功能-This procedure is used VHDL hardware descr iption languages, the realization of the four full-adder function
w
- 用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.
2008619105258431
- 九个输入，一个输出，实现四位全加器，四位全加器的功能-9 input, 1 output, to achieve four full-adder, four full-adder function
four_adder
- 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
4add
- 一位全加器和四位全加器，EDA板图设计，并且有图片。
vhdlcoder
- 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160
fadder_4
- 利用quartus9.0中元器件模块设计的四位全加器，能运行出结果(Quartus9.0 binary device using the design of four bit full adder, can run the results)
fadder_4v
- 利用quartus9.0中verilog语言实现的四位全加器，亲测有效(Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective)
xor4b
- 实现四位全加器，为初学者提供参考说明，对VHDL语言有一定了解(it's a addler of four bits,which is designed for the new learner of VHDL language)