文件名称:xcv
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verilog编写的状态机检测00100序列.
实现 input:...011000010010000...
output:...000000000100100...
并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working
实现 input:...011000010010000...
output:...000000000100100...
并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working
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下载文件列表
压缩包 : 107215780xcv.rar 列表 xcv\test.v xcv\work\xcv\verilog.asm xcv\work\xcv\_primary.dat xcv\work\xcv\_primary.vhd xcv\work\xcv_@top\verilog.asm xcv\work\xcv_@top\_primary.dat xcv\work\xcv_@top\_primary.vhd xcv\work\_info xcv\xcv.v xcv\work\xcv xcv\work\xcv_@top xcv\work xcv