文件名称:pluse_delay
介绍说明－－下载内容均来自于网络，请自行研究使用
利用VHDL语言实现单稳触发电路，稳态时间为系统时钟的整数倍。-using VHDL-trigger circuit stability, steady time for the whole system clock several times.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 39709576pluse_delay.rar 列表 pluse_delay pluse_delay\pluse_delay.acf pluse_delay\pluse_delay.vhd pluse_delay\U3633468.DLS pluse_delay\U8440066.DLS pluse_delay\U0770890.DLS pluse_delay\pluse_delay.cnf pluse_delay\PLUSE_DELAY.sym pluse_delay\LIB.DLS pluse_delay\pluse_delay(1).cnf pluse_delay\pluse_delay(2).cnf pluse_delay\pluse_delay(3).cnf pluse_delay\pluse_delay(4).cnf pluse_delay\pluse_delay.hif pluse_delay\pluse_delay.pin pluse_delay\pluse_delay.fit pluse_delay\pluse_delay.ndb pluse_delay\pluse_delay.snf pluse_delay\pluse_delay.sof pluse_delay\pluse_delay.pof pluse_delay\pluse_delay.hex pluse_delay\pluse_delay.ttf pluse_delay\pluse_delay.scf pluse_delay\pluse_delay.mmf pluse_delay\pluse_delay.rpt