文件名称:pluse_delay
介绍说明－－下载内容均来自于网络，请自行研究使用
利用VHDL语言实现单稳触发电路，稳态时间为系统时钟的整数倍。-using VHDL-trigger circuit stability, steady time for the whole system clock several times.
相关搜索： vhdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pluse_delay
...........\LIB.DLS
...........\pluse_delay.acf
...........\pluse_delay.fit
...........\pluse_delay.hex
...........\pluse_delay.hif
...........\pluse_delay.mmf
...........\pluse_delay.ndb
...........\pluse_delay.pin
...........\pluse_delay.pof
...........\pluse_delay.rpt
...........\pluse_delay.scf
...........\pluse_delay.snf
...........\pluse_delay.sof
...........\PLUSE_DELAY.sym
...........\pluse_delay.ttf
...........\pluse_delay.vhd
...........\U0770890.DLS
...........\U3633468.DLS
...........\U8440066.DLS
...........\LIB.DLS
...........\pluse_delay.acf
...........\pluse_delay.fit
...........\pluse_delay.hex
...........\pluse_delay.hif
...........\pluse_delay.mmf
...........\pluse_delay.ndb
...........\pluse_delay.pin
...........\pluse_delay.pof
...........\pluse_delay.rpt
...........\pluse_delay.scf
...........\pluse_delay.snf
...........\pluse_delay.sof
...........\PLUSE_DELAY.sym
...........\pluse_delay.ttf
...........\pluse_delay.vhd
...........\U0770890.DLS
...........\U3633468.DLS
...........\U8440066.DLS