压缩包 : 117143189hjs verilog.rar 列表
Verilog example source\chap9\bidir.v
Verilog example source\chap9\bidir2.v
Verilog example source\chap9\code_83.v
Verilog example source\chap9\decode47.v
Verilog example source\chap9\decoder_38.v
Verilog example source\chap9\dff.v
Verilog example source\chap9\dff1.v
Verilog example source\chap9\dff2.v
Verilog example source\chap9\encoder8_3.v
Verilog example source\chap9\gate1.v
Verilog example source\chap9\gate2.v
Verilog example source\chap9\gate3.v
Verilog example source\chap9\jk_ff.v
Verilog example source\chap9\johnson.v
Verilog example source\chap9\latch_1.v
Verilog example source\chap9\latch_2.v
Verilog example source\chap9\latch_8.v
Verilog example source\chap9\mac.v
Verilog example source\chap9\mac_tp.v
Verilog example source\chap9\map_lpm_ram.v
Verilog example source\chap9\mpc.v
Verilog example source\chap9\mpc_tp.v
Verilog example source\chap9\mux_case.v
Verilog example source\chap9\mux_if.v
Verilog example source\chap9\parity.v
Verilog example source\chap9\ram256x8.v
Verilog example source\chap9\reg8.v
Verilog example source\chap9\rom.v
Verilog example source\chap9\serial_pal.v
Verilog example source\chap9\shifter.v
Verilog example source\chap9\tri_1.v
Verilog example source\chap9\tri_2.v
Verilog example source\chap9\updown_count.v
Verilog example source\chap9
Verilog example source\chap8\add8_tp.v
Verilog example source\chap8\carry_udp.v
Verilog example source\chap8\carry_udpx1.v
Verilog example source\chap8\carry_udpx2.v
Verilog example source\chap8\count8_tp.v
Verilog example source\chap8\delay.v
Verilog example source\chap8\dff.v
Verilog example source\chap8\dff_udp.v
Verilog example source\chap8\latch.v
Verilog example source\chap8\mult_tp.v
Verilog example source\chap8\mux31.v
Verilog example source\chap8\mux_tp.v
Verilog example source\chap8\random_tp.v
Verilog example source\chap8\rom.v
Verilog example source\chap8\test1.v
Verilog example source\chap8\test2.v
Verilog example source\chap8\time_dif.v
Verilog example source\chap8
Verilog example source\chap7\add4_1.v
Verilog example source\chap7\add4_2.v
Verilog example source\chap7\add4_3.v
Verilog example source\chap7\count4.v
Verilog example source\chap7\full_add1.v
Verilog example source\chap7\full_add2.v
Verilog example source\chap7\full_add3.v
Verilog example source\chap7\full_add4.v
Verilog example source\chap7\full_add5.v
Verilog example source\chap7\half_add1.v
Verilog example source\chap7\half_add2.v
Verilog example source\chap7\half_add3.v
Verilog example source\chap7\half_add4.v
Verilog example source\chap7\mux2_1a.v
Verilog example source\chap7\mux2_1b.v
Verilog example source\chap7\mux2_1c.v
Verilog example source\chap7\mux4_1a.v
Verilog example source\chap7\mux4_1b.v
Verilog example source\chap7\mux4_1c.v
Verilog example source\chap7\mux4_1d.v
Verilog example source\chap7
Verilog example source\chap6\alutask.v
Verilog example source\chap6\alu_tp.v
Verilog example source\chap6\code_83.v
Verilog example source\chap6\count.v
Verilog example source\chap6\funct.v
Verilog example source\chap6\funct_tp.v
Verilog example source\chap6\paral1.v
Verilog example source\chap6\paral2.v
Verilog example source\chap6\serial1.v
Verilog example source\chap6\serial2.v
Verilog example source\chap6
Verilog example source\chap5\adder.v
Verilog example source\chap5\adder16.v
Verilog example source\chap5\alu.v
Verilog example source\chap5\block.v
Verilog example source\chap5\buried_ff.v
Verilog example source\chap5\compile.v
Verilog example source\chap5\count.v
Verilog example source\chap5\count60.v
Verilog example source\chap5\decode4_7.v
Verilog example source\chap5\loop1.v
Verilog example source\chap5\loop2.v
Verilog example source\chap5\loop3.v
Verilog example source\chap5\mult_for.v
Verilog example source\chap5\mult_repeat.v
Verilog example source\chap5\mux21_1.v
Verilog example source\chap5\mux21_2.v
Verilog example source\chap5\mux4_1.v
Verilog example source\chap5\mux_casez.v
Verilog example source\chap5\non_block.v
Verilog example source\chap5\test.v
Verilog example source\chap5\voter7.v
Verilog example source\chap5\wave1.v
Verilog example source\chap5\wave2.v
Verilog example source\chap5
Verilog example source\chap3\adder4.v
Verilog example source\chap3\adder_tp.v
Verilog example source\chap3\aoi.v
Verilog example source\chap3\count4.v
Verilog example source\chap3\count4_tp.v
Verilog example source\chap3
Verilog example source\chap12\add_ahead.v
Verilog example source\chap12\add_bx.v
Verilog example source\chap12\add_jl.v
Verilog example source\chap12\add_tree.v
Verilog example source\chap12\correlator.v
Verilog example source\chap12\crc.v
Verilog example source\chap12\cycle.v
Verilog example source\chap12\decoder1.v
Verilog example source\chap12\decoder2.v
Verilog example source\chap12\fir.v
Verilog example source\chap12\linear.v
Verilog example source\chap12\mult.v
Verilog example source\chap12\mult4x4.v
Verilog example source\chap12
Verilog example source\chap11\account.v
Verilog example source\chap11\clock.v
Verilog example source\chap11\count10.v
Verilog example source\chap11\fre_ctrl.v
Verilog example source\chap11\latch_16.v
Verilog example source\chap11\paobiao.v
Verilog example source\chap11\sell.v
Verilog example source\chap11\song.v
Verilog example source\chap11\traffic.v
Verilog example source\chap11
Verilog example source\chap10\acc.v
Verilog example source\chap10\accn.v
Verilog example source\chap10\add8.v
Verilog example source\chap10\adder8.v
Verilog example source\chap10\block1.v
Verilog example source\chap10\block2.v
Verilog example source\chap10\block3.v
Verilog example source\chap10\block4.v
Verilog example source\chap10\control.v
Verilog example source\chap10\fsm.v
Verilog example source\chap10\longframe1.v
Verilog example source\chap10\longframe2.v
Verilog example source\chap10\pipeline.v
Verilog example source\chap10\reg8.v
Verilog example source\chap10\resource1.v
Verilog example source\chap10\resource2.v
Verilog example source\chap10
Verilog example source