文件名称:VHDL-and-Verilog-code
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82个逻辑器件的VHDL和Verilog源码实例，可直接使用。-VHDL and Verilog source code examples of the 82 logic devices can be used directly.
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下载文件列表
82 Examples for VHDL and Verilog code
.....................................\12位寄存器_verilog.v
.....................................\16450异步通讯接口，ALDEC提供.vhd
.....................................\16450异步通讯接口，ALDEC提供_verilog.v
.....................................\4位乘法器_vhdl.txt
.....................................\4位除法器_vhdl.txt
.....................................\fifo_vhdl.txt
.....................................\LED七段译码 _vhdl.txt
.....................................\stop_watch.vhd
.....................................\VHDL_计数器及testbench.txt
.....................................\一个VHDL实现的测频计.vhd
.....................................\一个同步状态机_verilog.txt
.....................................\一个游戏程序mancala_vhdl.vhd
.....................................\一个简单的UART_verilog.v
.....................................\一个简单的UART_vhdl.vhd
.....................................\一个简单的状态机 _altera_vhdl.vhd
.....................................\一个简单的状态机_altera_verilog.v
.....................................\三人表决器（三种不同的描述方式）_vhdl.txt
.....................................\三态总线_vhdl.txt
.....................................\二进制到BCD码转换_verilog.txt
.....................................\二进制到BCD码转换_vhd.txt
.....................................\二进制到格雷码转换_verilog.txt
.....................................\二进制到格雷码转换_vhdl.txt
.....................................\伪随机数产生器_vhdl.vhd
.....................................\伪随机比特发生器_vhdl.txt
.....................................\使用列举类型的状态机_vhdl.vhd
.....................................\使用变量的状态机_vhdl.txt
.....................................\元件例化与层次设计_verilog.txt
.....................................\元件例化与层次设计_vhdl.txt
.....................................\加法器描述_vhdl.txt
.....................................\加法器源程序_verilog.v
.....................................\加法器源程序_vhdl.vhd
.....................................\加法器：generate语句的应用_vhdl.txt
.....................................\双2－4译码器：74139_vhdl.txt
.....................................\双向总线_vhdl.txt
.....................................\双向管脚（clocked bidirectional pin）_verilog.txt
.....................................\各种功能的计数器_altera_vhdl.vhd
.....................................\各种类型计数器 _altera_verilog.v
.....................................\四D触发器：74175_vhdl .txt
.....................................\地址译码（for m68008）_vhdl.txt
.....................................\多路选择器 （使用case语句）_vhdl .txt
.....................................\多路选择器（MUX）_verilog.txt
.....................................\多路选择器（使用if－else语句）_vhdl.txt
.....................................\多路选择器（使用select语句）_vhdl.txt
.....................................\多路选择器（使用when－else语句）_vhdl.txt
.....................................\将16进制转化为std_logic_vhdl.txt
.....................................\布斯乘法器__vhdl.txt
.....................................\带load、clr等功能的寄存器_vhdl.vhd
.....................................\带load，clr等功能的寄存器_verilog.v
.....................................\带三态输出的8位D寄存器：74374_374_vhdl.txt
.....................................\带同步复位的状态机_vhdl.txt
.....................................\带莫尔_米勒输出的状态机_vhdl.txt
.....................................\并口通讯代码（调试通过）.txt
.....................................\无符号数到整数的转换_altera_vhdl.vhd
.....................................\最高优先级编码器_vhdl .txt
.....................................\条件赋值：使用when else语句_vhdl.vhd
.....................................\条件赋值：使用列举类型_vhdl.vhd
.....................................\条件赋值：使用多路选择器_vhdl.vhd
.....................................\步进电机控制器_vhdl.vhd
.....................................\汉明纠错吗编码器_vhdl.txt
.....................................\汉明纠错吗译码器_vhdl.txt
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