文件名称:UART-FPGA

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-08-19
  • 文件大小:
  • 9.47mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • shenx*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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verilog的UART通信,解决了接受过程中的毛刺问题,将接受和发送两个过程独立开来-The UART verilog communication, solve problems receiving glitches during the process of receiving and sending two separate open
(系统自动生成,下载前可以参看下载内容)

下载文件列表





UART-FPGA

.........\db

.........\..\altsyncram_2hq1.tdf

.........\..\altsyncram_as14.tdf

.........\..\altsyncram_gs14.tdf

.........\..\altsyncram_igq1.tdf

.........\..\altsyncram_is14.tdf

.........\..\altsyncram_ogq1.tdf

.........\..\altsyncram_qgq1.tdf

.........\..\altsyncram_qs14.tdf

.........\..\cmpr_5cc.tdf

.........\..\cmpr_9cc.tdf

.........\..\cmpr_acc.tdf

.........\..\cntr_2ci.tdf

.........\..\cntr_gui.tdf

.........\..\cntr_qbi.tdf

.........\..\cntr_sbi.tdf

.........\..\cntr_tbi.tdf

.........\..\cntr_u4j.tdf

.........\..\cntr_vbi.tdf

.........\..\decode_rqf.tdf

.........\..\logic_util_heursitic.dat

.........\..\mux_9oc.tdf

.........\..\prev_cmp_UART.map.qmsg

.........\..\prev_cmp_UART.qmsg

.........\..\UART.db_info

.........\..\UART.ipinfo

.........\..\UART.sld_design_entry.sci

.........\greybox_tmp

.........\...........\cbx_args.txt

.........\incremental_db

.........\..............\compiled_partitions

.........\..............\...................\UART.autoh_e4eb1.map.dpi

.........\..............\...................\UART.autoh_e4eb1.map.kpt

.........\..............\...................\UART.autoh_e4eb1.map.logdb

.........\..............\...................\UART.autos_3e921.map.dpi

.........\..............\...................\UART.autos_3e921.map.kpt

.........\..............\...................\UART.autos_3e921.map.logdb

.........\..............\...................\UART.db_info

.........\..............\...................\UART.root_partition.cmp.dfp

.........\..............\...................\UART.root_partition.cmp.kpt

.........\..............\...................\UART.root_partition.cmp.logdb

.........\..............\...................\UART.root_partition.map.atm

.........\..............\...................\UART.root_partition.map.dpi

.........\..............\...................\UART.root_partition.map.hdbx

.........\..............\...................\UART.root_partition.map.kpt

.........\..............\README

.........\kk.ppf

.........\kk.qip

.........\kk.v

.........\kk_bb.v

.........\PLL.ppf

.........\PLL.qip

.........\PLL.v

.........\pll1.cmp

.........\pll1.ppf

.........\pll1.qip

.........\pll1.vhd

.........\pll2.ppf

.........\pll2.qip

.........\pll2.v

.........\pll2_bb.v

.........\PLLJ_PLLSPE_INFO.txt

.........\PLL_bb.v

.........\rec.v

.........\rec.v.bak

.........\send.v

.........\send.v.bak

.........\serv_req_info.txt

.........\simulation

.........\..........\modelsim

.........\..........\........\modelsim.ini

.........\..........\........\msim_transcript

.........\..........\........\rtl_work

.........\..........\........\........\@u@a@r@t

.........\..........\........\........\........\verilog.prw

.........\..........\........\........\........\verilog.psm

.........\..........\........\........\........\_primary.dat

.........\..........\........\........\........\_primary.dbs

.........\..........\........\........\........\_primary.vhd

.........\..........\........\........\@u@a@r@t_@t@o@p

.........\..........\........\........\...............\verilog.prw

.........\..........\........\........\...............\verilog.psm

.........\..........\........\........\...............\_primary.dat

.........\..........\........\........\...............\_primary.dbs

.........\..........\........\........\...............\_primary.vhd

.........\..........\........\........\kk

.........\..........\........\........\..\verilog.prw

.........\..........\........\........\..\verilog.psm

.........\..........\........\........\..\_primary.dat

.........\..........\........\........\..\_primary.dbs

.........\..........\........\........\..\_primary.vhd

.........\..........\........\........\rec

.........\..........\........\........\...\verilog.prw

.........\..........\........\........\...\verilog.psm

.........\..........\........\........\...\_primary.dat

.........\..........\........\........\...\_primary.dbs

.........\..........\........\........\...\_primary.vhd

.........\..........\........\........\send

.........\..........\........\........\....\verilog.prw

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