文件名称:FPGA-digital-circuit-design

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  • 其它资源
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  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.5mb
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  • 0次
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  • 卢**
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< FPGA数字电子系统设计与开发实例导航> 一书的代码,FPGA数字电子系统设计与开发实例导航,用硬件描述语言编写的,I2C,UART,USB,VGA,CAN-BUS,网络等等的书籍配套原代码。。。。

使用方法:

1.拷贝到硬盘。

2.用ISE创建项目,分别加入各个代码文件,即可。-<FPGA digital electronic systems design and development examples of navigation> a book code, FPGA digital electronic systems design and development examples of navigation, using hardware descr iption languages, I2C, UART, USB, VGA, CAN-BUS, network books, etc. matching the original code. . . . Usage: 1. Copy to your hard disk. 2. With ISE to create the project, respectively, to the various code files, you can.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FPGA数字电子系统设计与开发实例导航

..................................\Chapter10 Sample

..................................\................\eth_clockgen.v

..................................\................\eth_cop.v

..................................\................\eth_crc.v

..................................\................\eth_defines.v

..................................\................\eth_fifo.v

..................................\................\eth_host.v

..................................\................\eth_maccontrol.v

..................................\................\eth_macstatus.v

..................................\................\eth_memory.v

..................................\................\eth_miim.v

..................................\................\eth_outputcontrol.v

..................................\................\eth_phy.v

..................................\................\eth_phy_defines.v

..................................\................\eth_random.v

..................................\................\eth_receivecontrol.v

..................................\................\eth_register.v

..................................\................\eth_registers.v

..................................\................\eth_rxaddrcheck.v

..................................\................\eth_rxcounters.v

..................................\................\eth_rxethmac.v

..................................\................\eth_rxstatem.v

..................................\................\eth_shiftreg.v

..................................\................\eth_spram_256x32.v

..................................\................\eth_top.v

..................................\................\eth_transmitcontrol.v

..................................\................\eth_txcounters.v

..................................\................\eth_txethmac.v

..................................\................\eth_txstatem.v

..................................\................\eth_wishbone.v

..................................\................\tb_cop.v

..................................\................\tb_ethernet.v

..................................\................\tb_ethernet_with_cop.v

..................................\................\tb_eth_defines.v

..................................\................\tb_eth_top.v

..................................\................\timescale.v

..................................\................\wb_bus_mon.v

..................................\................\wb_master32.v

..................................\................\wb_master_behavioral.v

..................................\................\wb_model_defines.v

..................................\................\wb_slave_behavioral.v

..................................\................\使用说明.txt

..................................\Chapter4 Sample

..................................\...............\I2C

..................................\...............\...\automake.log

..................................\...............\...\coregen.log

..................................\...............\...\coregen.prj

..................................\...............\...\I2C.dhp

..................................\...............\...\I2C.npl

..................................\...............\...\i2c_master_bit_ctrl.cmd_log

..................................\...............\...\i2c_master_bit_ctrl.lso

..................................\...............\...\i2c_master_bit_ctrl.ngc

..................................\...............\...\i2c_master_bit_ctrl.ngr

..................................\...............\...\i2c_master_bit_ctrl.prj

..................................\...............\...\i2c_master_bit_ctrl.stx

..................................\...............\...\i2c_master_bit_ctrl.syr

..................................\...............\...\i2c_master_bit_ctrl.v

..................................\...............\...\i2c_master_bit_ctrl.v.bak

..................................\...............\...\i2c_master_bit_ctrl_vhdl.prj

..................

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